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WM8781 Schematic ( PDF Datasheet ) - Wolfson Microelectronics

Teilenummer WM8781
Beschreibung Stereo ADC
Hersteller Wolfson Microelectronics
Logo Wolfson Microelectronics Logo 




Gesamt 21 Seiten
WM8781 Datasheet, Funktion
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24-Bit, 192kHz Stereo ADC
WM8781
DESCRIPTION
The WM8781 is a high performance, low cost stereo audio
ADC designed for recordable media applications.
The device offers stereo line level inputs along with two
control input pins (FORMAT, IWL) to allow operation of the
audio interface in three industry standard modes. An
internal op-amp is integrated on the front end of the chip to
accommodate analogue input signals greater than 1Vrms.
The device also has a high pass filter to remove residual
DC offsets.
WM8781 offers Master or Slave mode clocking schemes.
A control input pin M/S is used to allow Slave mode
operation or Master mode operation. A stereo 24-bit multi-
bit sigma-delta ADC is used with 128x, 64x or 32x over-
sampling, according to sample rate. Digital audio output
word lengths from 16-24 bits and sampling rates from 8kHz
to 192kHz are supported.
The device is a hardware controlled device and is supplied
in a 20-lead SSOP package.
BLOCK DIAGRAM
FEATURES
SNR 102dB (‘A’ weighted @ 48kHz)
THD -90dB (at –1dB)
Sampling Frequency: 8 – 192kHz
Master or Slave Clocking Mode
System Clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs, 768fs
Audio Data Interface Modes
- 16-24 bit I2S, 16-24 bit Left, 16-24 bit Right Justified
Supply Voltages
- Analogue 2.7 to 5.5V
- Digital core: 2.7V to 3.6V
20-lead SSOP package
APPLICATIONS
Recordable DVD Players
Personal Video Recorders
STB
Studio Audio Processing Equipment
WOLFSON MICROELECTRONICS plc
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Production Data, January 2012, Rev 4.5
Copyright 2012 Wolfson Microelectronics plc






WM8781 Datasheet, Funktion
WM8781
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions
DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode
unless otherwise stated.
PARAMETER
ADC Performance
Full Scale Input Signal Level
(for ADC 0dB Input)
Input resistance, using
recommended external resistor
network on p17.
Input capacitance
Signal to Noise Ratio
(see Terminology note 1,2,4)
Signal to Noise Ratio
(see Terminology note 1,2,4)
Total Harmonic Distortion
Dynamic Range
Channel Separation
(see Terminology note 4)
Channel Level Matching
Channel Phase Deviation
Power Supply Rejection Ratio
Digital Logic Levels (TTL Levels)
Input LOW level
SYMBOL TEST CONDITIONS
SNR
SNR
THD
DNR
A-weighted,
@ fs = 48kHz
Unweighted,
@ fs = 48kHz
A-weighted,
@ fs = 48kHz, AVDD =
3.3V
A-weighted,
@ fs = 96kHz
Unweighted,
@ fs = 96kHz
A-weighted,
@ fs = 96kHz, AVDD =
3.3V
1kHz, -1dB Full Scale
@ fs = 48kHz
1kHz, -1dB Full Scale
@ fs = 96kHz
1kHz, -1dB Full Scale
@ fs = 192kHz
-60dBFS
1kHz Input
PSRR
1kHz signal
1kHz signal
1kHz 100mVpp, applied
to AVDD, DVDD
VIL
MIN
93
93
93
TYP
1.0
10
20
102
100
100
99
99
99
-91
-91
-90
102
90
0.1
0.0001
50
MAX
UNIT
Vrms
k
pF
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Degree
dB
0.8 V
Input HIGH level
Input leakage current – digital pad
Input leakage current – digital
tristate input (Note 3)
Input capacitance
Output LOW
Output HIGH
VIH
VOL
VOH
IOL=1mA
IOH= -1mA
2.0
-1 ±0.2 +1
85
5
0.1 x DVDD
0.9 x DVDD
V
µA
µA
pF
V
V
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PD, January 2012, Rev 4.5
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WM8781 pdf, datenblatt
WM8781
Production Data
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 7 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 8 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
Figure 9 I2S Audio Interface (assuming n-bit word length)
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PD, January 2012, Rev 4.5
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