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WM8782 Schematic ( PDF Datasheet ) - Wolfson Microelectronics

Teilenummer WM8782
Beschreibung Stereo ADC
Hersteller Wolfson Microelectronics
Logo Wolfson Microelectronics Logo 




Gesamt 20 Seiten
WM8782 Datasheet, Funktion
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24-Bit, 192kHz Stereo ADC
WM8782
DESCRIPTION
The WM8782 is a high performance, low cost stereo audio
ADC designed for recordable media applications.
The device offers stereo line level inputs along with two
control input pins (FORMAT, IWL) to allow operation of the
audio interface in three industry standard modes. An
internal op-amp is integrated on the front end of the chip to
accommodate analogue input signals greater than 1Vrms.
The device also has a high pass filter to remove residual
DC offsets.
WM8782 offers Master or Slave mode clocking schemes.
A control input pin M/S is used to allow Slave mode
operation or Master mode operation. A stereo 24-bit multi-
bit sigma-delta ADC is used with 128x, 64x or 32x over-
sampling, according to sample rate. Digital audio output
word lengths from 16-24 bits and sampling rates from 8kHz
to 192kHz are supported.
The device is a hardware controlled device and is supplied
in a 20-lead SSOP package.
The device is available over a functional temperature range of
-40C to +85C
BLOCK DIAGRAM
FEATURES
SNR 100dB (‘A’ weighted @ 48kHz)
THD -93dB (at –1dB)
Sampling Frequency: 8 – 192kHz
Master or Slave Clocking Mode
System Clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs,
768fs
- Audio Data Interface Modes
16-24 bit I2S, 16-24 bit Left, 16-24 bit Right Justified
Supply Voltages
- Analogue: 2.7 to 5.5V
- Digital core: 2.7V to 3.6V
20-lead SSOP or 20-lead TSSOP package
Accelerated Lifetime Screened Devices available.
APPLICATIONS
Recordable DVD Players
Personal Video Recorders
STB
Studio Audio Processing Equipment
Automotive
WOLFSON MICROELECTRONICS plc
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Production Data, April 2010, Rev 4.7
Copyright 2010 Wolfson Microelectronics plc






WM8782 Datasheet, Funktion
WM8782
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Digital supply range
Analogue supply range
Ground
Operating temperature range
SYMBOL
DVDD
AVDD
DGND,AGND
TA
TEST CONDITIONS
WM8782SEDS,
WM8782SEDS/R
WM8782SEDS,
WM8782SEDS/R
WM8782SEDS,
WM8782SEDS/R
Notes:
1. Digital supply DVDD must never be more than 0.3V greater than AVDD.
MIN
2.7
2.7
-40
Production Data
TYP
MAX
UNIT
3.6 V
5.5 V
0V
+85 C
ELECTRICAL CHARACTERISTICS
Test Conditions
DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode
unless otherwise stated.
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC Performance – WM8782SEDS, WM8782SEDS/R (+25˚C)
Full Scale Input Signal Level
(for ADC 0dB Input)
1.0 Vrms
Input resistance, using
recommended external resistor
network on p22.
10 k
Input capacitance
20 pF
Signal to Noise Ratio
SNR
weighted,
93 100
(see Terminology note 1,2,4)
@ fs = 48kHz
dB
Unweighted,
@ fs = 48kHz
98
dB
weighted,
@ fs = 48kHz,
AVDD = 3.3V
98
dB
Signal to Noise Ratio
(see Terminology note 1,2,4)
SNR
weighted,
@ fs = 96kHz
98
dB
Unweighted,
@ fs = 96kHz
98
dB
weighted,
98 dB
@ fs = 96kHz
AVDD = 3.3V
Total Harmonic Distortion
THD
1kHz, -1dB Full Scale
@ fs = 48kHz
-93
dB
1kHz, -1dB Full Scale
@ fs = 96kHz
-93
dB
1kHz, -1dB Full Scale
@ fs = 192kHz
-92
dB
Dynamic Range
DNR
-60dBFS
93 100
dB
Channel Separation
(see Terminology note 4)
1kHz Input
90 dB
Channel Level Matching
1kHz signal
0.1 dB
Channel Phase Deviation
1kHz signal
0.0001
Degree
Power Supply Rejection Ratio
PSRR
1kHz 100mVpp, applied
to AVDD, DVDD
50
dB
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PD, April 2010, Rev 4.7
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WM8782 pdf, datenblatt
WM8782
DIGITAL AUDIO INTERFACE
The digital audio interface uses three pins:
DOUT: ADC data output
LRCLK: ADC data alignment clock
BCLK: Bit clock, for synchronisation
Production Data
The digital audio interface takes the data from the internal ADC digital filters and places it on DOUT
and LRCLK. DOUT is the formatted digital audio data stream output from the ADC digital filters with
left and right channels multiplexed together. LRCLK is an alignment clock that controls whether Left
or Right channel data is present on the DOUT line. DOUT and LRCLK are synchronous with the
BCLK signal with each data bit transition signified by a BCLK high to low transition. DOUT is always
an output. BCLK and LRCLK maybe an inputs or outputs depending whether the device is in Master
or Slave mode. (see Master and Slave Mode Operation, below).
Three different audio data formats are supported:
Left justified
Right justified
I2S
MASTER AND SLAVE MODE OPERATION
The WM8782 can be configured as either a master or slave mode device. As a master device the
WM8782 generates BCLK and LRCLK and thus controls sequencing of the data transfer on DOUT. In
slave mode, the WM8782 responds with data to clocks it receives over the digital audio interface. The
mode can be selected by setting the MS input pin (see Table 6 Master/Slave selection below).
Master and slave modes are illustrated below.
Figure 6 Master Mode
Figure 7 Slave Mode
PIN
M/S
DESCRIPTION
Master/Slave Selection
0 = Slave Mode
1= Master Mode
Table 6 Master/Slave selection
AUDIO INTERFACE CONTROL
The Input Word Length and Audio Format mode can be selected by using IWL and FORMAT pins.
PIN
IWL
FORMAT
DESCRIPTION
Word Length
0 = 16 bit
1 = 20 bit
Z = 24 bit
Audio Mode Select
0 = RJ
1 = LJ
Z = I2S
Table 7 Audio Data Format Control
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PD, April 2010, Rev 4.7
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