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WM8718 Schematic ( PDF Datasheet ) - Wolfson Microelectronics

Teilenummer WM8718
Beschreibung 24 Bit Differential Stereo DAC
Hersteller Wolfson Microelectronics
Logo Wolfson Microelectronics Logo 




Gesamt 30 Seiten
WM8718 Datasheet, Funktion
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WM8718
24 Bit Differential Stereo DAC with Volume Control
DESCRIPTION
FEATURES
The WM8718 is a high performance differential stereo DAC
designed for audio applications such as DVD, home theatre
systems and digital TV. The WM8718 supports PCM data
input word lengths from 16 to 32-bits and sampling rates up
to 192kHz. The WM8718 consists of a serial interface port,
digital interpolation filters, multi-bit sigma delta modulators
and differential stereo DAC in a small 20-lead SSOP
package or 24-lead QFN package. The WM8718 includes a
digitally controllable mute, an attenuate function and zero
flag output for each channel.
The 3-wire serial control port provides access to a wide
range of features including on-chip mute, attenuation and
phase reversal.
The WM8718 is an ideal device to interface to AC-3,
DTS, and MPEG audio decoders for surround sound
applications, or for use in DVD players including those
supporting DVD-A.
24 bit Stereo DAC
Fully Differential Voltage Outputs
Audio Performance
- 111dB SNR (‘A’ weighted @ 48kHz) DAC
- -100dB THD
DAC Sampling Frequency: 8kHz - 192kHz
3 Wire Serial Control Interface
Programmable Audio Data Interface Modes
- I2S, Left, Right Justified, DSP
- 16/20/24/32 bit Word Lengths
Independent Digital Volume Control on Each Channel with
127.5dB Range in 0.5dB Steps
Independent Zero Flag Outputs
3.0V - 5.5V Supply Operation
20-lead SSOP Package or 24-lead QFN Package
APPLICATIONS
BLOCK DIAGRAM
CD, DVD, and DVD-Audio Players
Home theatre systems
www.DataSheet4U.comProfessional mixing desks
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WM8718
CONTROL
INTERFACE
ZEROFR
ZEROFL
BCKIN
LRCIN
DIN
AUDIO
INTERFACE
ATT/
MUTE
ATT/
MUTE
DIGITAL
FILTERS
SIGMA
DELTA
MODULATOR
SIGMA
DELTA
MODULATOR
DAC
DAC
VOUTRP
VOUTRN
VOUTLP
VOUTLN
VMID
WOLFSON MICROELECTRONICS plc
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Production Data, November 2006, Rev 4.3
Copyright ©2006 Wolfson Microelectronics plc






WM8718 Datasheet, Funktion
WM8718
PIN DESCRIPTION – 24 LEAD QFN
PIN NAME
TYPE
1 DVDD
Supply
2 DGND
Supply
3 AVDD
Supply
4 VREFP
Supply
5 VREFN
Supply
6 AGND
Supply
7 VMID
Analogue Output
8 VOUTRP
Analogue Output
9 VOUTRN
Analogue Output
10 VOUTLN
Analogue Output
11 VOUTLP
Analogue Output
12 NC
No Connect
13 NC
No Connect
14 LATCH
Digital Input P.U.
15 SDIN
Digital Input
16 SCLK
Digital Input P.D.
17
ZEROFR
Digital Output (Open drain)
18 NC
No Connect
19
ZEROFL
Digital Output (Open drain)
20 MCLK
Digital Input
21 BCLKIN
Digital Input
22 DIN
Digital Input
23 LRCIN
Digital Input
24 NC
No Connect
DESCRIPTION
Positive Digital Supply
Ground Digital Supply
Positive Analogue Supply
Positive DAC reference Supply
Negative DAC reference Supply
Ground Analogue Supply
Mid Rail Decoupling Point
Right Channel DAC Output Positive
Right Channel DAC Output Negative
Left Channel DAC Output Negative
Left Channel DAC Output Positive
No Connect
No Connect
Serial Control Load Input
Serial Control Data Input
Serial Control Data Input Clock
Infinite ZERO Detect Flag for Right Channel
No Connect
Infinite ZERO Detect Flag for Left Channel
Master Clock Input
PCM Audio Data Bit Clock Input
PCM Serial Audio Data Input
PCM DAC Sample Rate Clock Input
No Connect
Production Data
Note:
1. Digital input pins have Schmitt trigger input buffers. Pins marked `P.U.` or `P.D.` have an internal pull-up or pull-down
resistor.
2. It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
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PD Rev 4.3 November 2006
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WM8718 pdf, datenblatt
WM8718
INTERNAL POWER ON RESET CIRCUIT
Production Data
Figure 4 Internal Power On Reset Circuit Schematic
The WM8718 includes an internal Power On Reset Circuit which is used reset the digital logic into
a default state after power up.
Figure 4 shows a schematic of the internal POR circuit. The POR circuit is powered from AVDD.
The circuit monitors DVDD and VMID and asserts PORB low if DVDD or VMID are below the
minimum threshold Vpor_off.
On power up, the POR circuit requires AVDD to be present to operate. PORB is asserted low until
AVDD and DVDD and VMID are established. When AVDD, DVDD, and VMID have been
established, PORB is released high, all registers are in their default state and writes to the digital
interface may take place.
On power down, PORB is asserted low whenever DVDD or VMID drop below the minimum
threshold Vpor_off.
If AVDD is removed at any time, the internal Power On Reset circuit is powered down and PORB
will follow AVDD.
In most applications the time required for the device to release PORB high will be determined by
the charge time of the VMID node.
Figure 5 Typical Power Up Sequence Where DVDD is Powered Before AVDD
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PD Rev 4.3 November 2006
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