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WM8590 Schematic ( PDF Datasheet ) - Wolfson Microelectronics

Teilenummer WM8590
Beschreibung 192kHz Stereo CODEC
Hersteller Wolfson Microelectronics
Logo Wolfson Microelectronics Logo 




Gesamt 30 Seiten
WM8590 Datasheet, Funktion
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24-bit, 192kHz Stereo CODEC
WM8590
DESCRIPTION
FEATURES
The WM8590 is a high performance, stereo audio codec with
differential inputs and outputs. It is ideal for surround sound
processing applications for home hi-fi, DVD-RW and other
audio visual equipment.
Audio Performance
110dB SNR (‘A’ weighted @ 48kHz) DAC
102dB SNR (‘A’ weighted @ 48kHz) ADC
DAC Sampling Frequency: 32kHz – 192kHz
The stereo 24-bit multi-bit sigma delta ADC has programmable
gain with limiting control. Digital audio output word lengths from
16-32 bits and sampling rates from 32kHz to 96kHz are
supported.
A stereo multi-bit sigma delta DAC is used with digital audio
input word lengths from 16-32 bits and sampling rates from
32kHz to 192kHz.
The WM8590 supports fully independent sample rates for the
ADC and DAC. The audio data interface supports I2S, left
justified, right justified and DSP formats.
The device is controlled in software via a 3 wire serial interface
which provides access to all features including volume controls,
mutes, and de-emphasis facilities. The device is available in a
28-lead SSOP package.
ADC Sampling Frequency: 32kHz – 96kHz
Stereo ADC input analogue gain adjust from +24dB to –21dB in
0.5dB steps
ADC digital gain from -21.5dB to -103dB in 0.5dB steps
Programmable Limiter on ADC input.
Stereo DAC with differential analogue line outputs.
3-Wire SPI Compatible Control Interface
Master or Slave Clocking Mode
Programmable Audio Data Interface Modes
I2S, Left, Right Justified or DSP
16/20/24/32 bit Word Lengths
4.5V to 5.5V Analogue, 2.7V to 3.6V Digital supply Operation
28-lead SSOP Package
APPLICATIONS
www.DataSheet4U.com
BLOCK DIAGRAM
Surround Sound AV Processors and Hi-Fi systems
DVD-RW
WOLFSON MICROELECTRONICS plc
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Production Data, January 2006, Rev 4.0
Copyright 2006 Wolfson Microelectronics plc






WM8590 Datasheet, Funktion
WM8590
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Digital supply range
Analogue supply range
Ground
Difference DGND to AGND
SYMBOL
DVDD
AVDD, DACREFP
AGND, DGND,
DACREFN,
ADCREFGND
TEST CONDITIONS
MIN
2.7
4.5
-0.3
TYP
3.3
5
0
0
Note:
1. Digital supply DVDD must never be more than 0.3V greater than AVDD in normal operation.
2. It is possible to hold the device in reset with AVDD=0V and DVDD=3.3V.
Production Data
MAX
3.6
5.5
UNIT
V
V
V
+0.3 V
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
0.3 x DVDD
V
Input HIGH level
VIH
0.7 x DVDD
V
Output LOW
VOL IOL=1mA
0.1 x DVDD
V
Output HIGH
VOH
IOH=1mA
0.9 x DVDD
V
Digital Input Leakage Current
0.9 µA
Digital Input Leakage
Capacitance
5 pF
Analogue Reference Levels
Reference voltage
VVMID
Potential divider resistance
RVMID
DAC Performance (Load = 10k, 50pF)
AVDD/2
50
V
k
0dBFs Full scale output voltage
2.0 x
Vrms
AVDD/5
SNR (Note 1,2)
SNR
A-weighted,
100 110
dB
@ fs = 48kHz
SNR (Note 1,2)
SNR
A-weighted
109
dB
@ fs = 96kHz
Dynamic Range (Note 2)
DNR
A-weighted, -60dB
full scale input
100
110
dB
Total Harmonic Distortion
THD
1kHz, 0dBFs
-97 -87
dB
DAC channel separation
130 dB
Channel Level Matching
1kHz signal 0.1 dB
Channel Phase Deviation
1kHz signal
0.04 Degree
Power Supply Rejection Ratio
PSRR
1kHz 100mVpp
50
dB
20Hz to 20kHz
100mVpp
45
dB
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PD Rev 4.0 January 2006
6

6 Page









WM8590 pdf, datenblatt
WM8590
3-WIRE MPU INTERFACE TIMING
Production Data
Figure 6 SPI Compatible (3-wire) Control Interface Input Timing
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated
PARAMETER
CL rising edge to CE rising edge
CL pulse cycle time
CL pulse width low
CL pulse width high
DI to CL set-up time
CL to DI hold time
CE falling edge to CL rising edge
CE pulse width high
CE rising to CL rising
SYMBOL
tSCS
tSCY
tSCL
tSCH
tDSU
tDHO
tCSC
tCSH
tCSS
MIN
60
80
30
30
20
20
20
20
20
Table 4 3-wire SPI Compatible Control Interface Input Timing Information
TYP MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
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PD Rev 4.0 January 2006
12

12 Page





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