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Teilenummer | WM8591 |
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Beschreibung | Stereo CODEC | |
Hersteller | Wolfson Microelectronics | |
Logo | ||
Gesamt 30 Seiten w
24-bit, 192kHz Stereo CODEC
WM8591
DESCRIPTION
FEATURES
The WM8591 is a high performance, stereo audio CODEC with
single-ended inputs and differential outputs. It is ideal for
surround sound processing applications for home hi-fi, DVD-
RW and other audio visual equipment.
•
•
Audio Performance
− 110dB SNR (‘A’ weighted @ 48kHz) DAC
− 102dB SNR (‘A’ weighted @ 48kHz) ADC
DAC Sampling Frequency: 32kHz – 192kHz
The stereo 24-bit multi-bit sigma delta ADC has programmable
gain with limiting control. Digital audio output word lengths from
16-32 bits and sampling rates from 32kHz to 96kHz are
supported.
A stereo multi-bit sigma delta DAC is used with digital audio
input word lengths from 16-32 bits and sampling rates from
32kHz to 192kHz.
The WM8591 supports fully independent sample rates for the
ADC and DAC. The audio data interface supports I2S, left
justified, right justified and DSP formats.
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•
•
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•
•
•
•
The device is controlled in software via a 2-wire serial interface
which provides access to all features including volume controls,
mutes, and de-emphasis facilities. The device is available in a
28-lead SSOP package.
•
•
ADC Sampling Frequency: 32kHz – 96kHz
Stereo ADC input analogue gain adjust from +24dB to –21dB in
0.5dB steps
ADC digital gain from -21.5dB to -103dB in 0.5dB steps
Programmable Limiter on ADC input.
Stereo DAC with differential analogue line outputs.
2-wire Serial Control Interface
Master or Slave Clocking Mode
Programmable Audio Data Interface Modes
− I2S, Left, Right Justified or DSP
− 16/20/24/32 bit Word Lengths
4.5V to 5.5V Analogue, 2.7V to 3.6V Digital supply Operation
28-lead SSOP Package
APPLICATIONS
www.DataSheet4U.com
BLOCK DIAGRAM
• Surround Sound AV Processors and Hi-Fi systems
• DVD-RW
WOLFSON MICROELECTRONICS plc
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Production Data, December 2005, Rev 4.0
Copyright 2005 Wolfson Microelectronics plc
WM8591
Production Data
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Digital supply range
Analogue supply range
Ground
Difference DGND to AGND
SYMBOL
DVDD
AVDD, DACREFP
AGND, DGND,
DACREFN,
ADCREFGND
TEST CONDITIONS
MIN
2.7
4.5
-0.3
TYP
3.3
5
0
0
Notes:
1. Digital supply DVDD must never be more than 0.3V greater than AVDD in normal operation.
2. It is possible to hold the device in reset with AVDD=0V and DVDD=3.3V.
MAX
3.6
5.5
+0.3
UNIT
V
V
V
V
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (CMOS Levels)
Input LOW level
Input HIGH level
VIL
VIH
0.7 x DVDD
0.3 x DVDD
V
V
Output LOW
Output HIGH
Digital Input Leakage Current
VOL
VOH
IOL=1mA
IOH=1mA
0.1 x DVDD
V
0.9 x DVDD
V
0.9 µA
Digital Input Leakage
Capacitance
5 pF
Analogue Reference Levels
Reference voltage
VVMID
Potential divider resistance
RVMID
DAC Performance (Load = 10kΩ, 50pF)
AVDD/2
50
V
kΩ
0dBFs Full scale output voltage
2.0 x
Vrms
AVDD/5
SNR (Note 1,2)
SNR
A-weighted,
105
110
dB
@ fs = 48kHz
SNR (Note 1,2)
SNR
A-weighted
109 dB
@ fs = 96kHz
Dynamic Range (Note 2)
DNR
A-weighted, -60dB
full scale input
105
110
dB
Total Harmonic Distortion
THD
1kHz, 0dBFs
-97 -90
dB
DAC channel separation
130 dB
Channel Level Matching
1kHz signal 0.1 dB
Channel Phase Deviation
1kHz signal
0.04 Degree
Power Supply Rejection Ratio
PSRR
1kHz 100mVpp
50
dB
20Hz to 20kHz
100mVpp
45
dB
ADC Performance
Input Signal Level (0dB)
1.0 x
Vrms
AVDD/5
SNR (Note 1,2)
SNR
A-weighted, 0dB gain
93
102
dB
@ fs = 48kHz
ADCMCLK2DAC=1
SNR (Note 1,2)
SNR
A-weighted, 0dB gain
99
dB
@ fs = 96kHz
64 x OSR
ADCMCLK2DAC=1
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PD Rev 4.0 December 2005
6
6 Page WM8591
CONTROL INTERFACE TIMING – 2-WIRE SERIALCONTROL
Production Data
Figure 6 Control Interface Timing – 2-Wire Serial Control Mode (MODE=0)
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated
PARAMETER
Program Register Input Information
CL Frequency
CL Low Pulse-Width
CL High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
DI, CL Rise Time
DI, CL Fall Time
Setup Time (Stop Condition)
Data Hold Time
Pulse width of spikes that will be suppressed
SYMBOL
t1
t2
t3
t4
t5
t6
t7
t8
t9
tps
MIN TYP MAX
0 526
1.3
600
600
600
100
300
300
600
900
05
Table 4 2-wire Control Interface Timing Information
UNIT
kHz
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
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PD Rev 4.0 December 2005
12
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ WM8591 Schematic.PDF ] |
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