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CAT25C09 Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT25C09
Beschreibung (CAT25C03 - CAT25C17) 1K/2K/4K/8K/16K SPI Serial CMOS EEPROM
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 12 Seiten
CAT25C09 Datasheet, Funktion
CAT25C11/03/05/09/17
1K/2K/4K/8K/16K SPI Serial CMOS EEPROM
FEATURES
s 10 MHz SPI compatible
s 1,000,000 program/erase cycles
s 1.8 to 6.0 volt operation
s 100 year data retention
s Hardware and software protection
s Low power CMOS technology
s SPI modes (0,0 & 1,1)*
s Commercial, industrial, automotive and extended
rtstemperature ranges
s Self-timed write cycle
s 8-pin DIP/SOIC, 8-pin TSSOP and 8-pin MSOP
s 16/32-byte page write buffer
s Write protection
– Protect first page, last page, any 1/4 array or
lower 1/2 array
DESCRIPTION
The CAT25C11/03/05/09/17 is a 1K/2K/4K/8K/16K-Bit
aSPI Serial CMOS EEPROM internally organized as
128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst’s
Padvanced CMOS Technology substantially reduces
device power requirements. The CAT25C11/03/05
features a 16-byte page write buffer. The 25C09/17
features a 32-byte page write buffer.The device operates
dvia the SPI bus serial interface and is enabled though a
Chip Select (CS). In addition to the Chip Select, the clock
input (SCK), data in (SI) and data out (SO) are required
to access the device. The HOLD pin may be used to
suspend any serial communication without resetting the
serial sequence. The CAT25C11/03/05/09/17 is designed
with software and hardware write protection features
including Block Write protection. The device is available
in 8-pin DIP, 8-pin SOIC, 8/14-pin TSSOP and 8-pin
MSOP packages.
ePIN CONFIGURATION
www.DataSheet4U.com
uMSOP Package (R, Z, GZ)* SOIC Package (S, V, GV) DIP Package (P, L, GL) TSSOP Package (U, Y, GY)
CS 1
SO 2
tinWP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
*CAT25C11/03 only
CS
SO
WP
VSS
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
CS
SO
WP
VSS
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
CS
SO
WP
VSS
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
nPIN FUNCTIONS
oPin Name
Function
cSO
SCK
Serial Data Output
Serial Clock
isWP Write Protect
VCC +1.8V to +6.0V Power Supply
DVSS Ground
BLOCK DIAGRAM
SENSE AMPS
SHIFT REGISTERS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SO
SI
CS
WP
HOLD
I/O
CONTROL
SPI
CONTROL
LOGIC
XDEC
EEPROM
ARRAY
SCK
CS Chip Select
BLOCK
SI Serial Data Input
PROTECT
LOGIC
HOLD
NC
Suspends Serial Input
No Connect
DATA IN
STORAGE
* Other SPI modes available on request.
STATUS
REGISTER
HIGH VOLTAGE/
TIMING CONTROL
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1017, Rev. L






CAT25C09 Datasheet, Funktion
CAT25C11/03/05/09/17
operation to the status register. The WP pin function is 03/05/09/17 is busy with a write operation. When set to
blocked when the WPEN bit is set to 0. Figure 10 illustrates
the WP timing sequence during a write operation.
1 a write cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only the WEL (Write
HOLD: Hold
Enable) bit indicates the status of the write enable latch.
When set to 1, the device is in a Write Enable state and
HOLD is the HOLD pin. The HOLD pin is used to pause
transmission to the CAT25C11/03/05/09/17 while in the
when set to 0 the device is in a Write Disable state. The
WEL bit can only be set by the WREN instruction and can
middle of a serial sequence without having to re-transmit be reset by the WRDI instruction.
entire sequence at a later time. To pause, HOLD must be
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication, HOLD is brought high, while SCK is low.
HOLD should be held high any time this function is not
rtsbeing used. HOLD may be tied high directly to VCCor tied
to VCC through a resistor. Figure 9 illustrates hold timing
sequence.
STATUS REGISTER
aThe Status Register indicates the status of the device.
PThe RDY (Ready) bit indicates whether the CAT25C11/
The BP0, BP1 and BP2 bits indicate which part of the
memory array is currently protected. These bits are set
by the user issuing the WRSR instruction. The user is
allowed to protect from one page to as much as half the
entire array. Once the three protection bits are set the
associated memory can be read but not written until the
protection bits are reset. These bits are non volatile.
The WPEN (Write Protect Enable) is an enable b it for the
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when WP is
low and WPEN bit is set to high. The user cannot write
to the status register, (including the block protect bits
Figure 2. WREN Instruction Timing
dCS
ueSK
tinSI 0 0 0 0 0 1 1 0
nSO
Note: Dashed Line= mode (1, 1) – – – –
oFigure 3. WRDI Instruction Timing
HIGH IMPEDANCE
cCS
DisSK
SI
SO
Note: Dashed Line= mode (1, 1) – – – –
Doc. No. 1017, Rev. L
0 0 0 0 0 1 00
HIGH IMPEDANCE
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

6 Page









CAT25C09 pdf, datenblatt
REVISION HISTORY
Date
Rev.
Reason
08/03/2004 J
Updated Features
Updated DC Operating Characteristics table & notes
07/08/2005 K
Update Features
Update Pin Configuration
09/22/2005 L
Update Reliability Characteristics
Update Ordering Information
Update Pin Configuration
d PartsCopyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
eDPP ™ AE2 ™ MiniPot™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
uissued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
tinPRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
nsituation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
olabeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
Disctypical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.caalyst-semiconductor.com
Publication #: 1017
Revison:
L
Issue date: 09/22/05

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