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What is CAT1027?

This electronic component, produced by the manufacturer "Catalyst Semiconductor", performs the same function as "(CAT1026 / CAT1027) Dual Voltage Supervisory Circuits".


CAT1027 Datasheet PDF - Catalyst Semiconductor

Part Number CAT1027
Description (CAT1026 / CAT1027) Dual Voltage Supervisory Circuits
Manufacturers Catalyst Semiconductor 
Logo Catalyst Semiconductor Logo 


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CAT1026, CAT1027
Dual Voltage Supervisory Circuits with
I2C Serial 2k-bit CMOS EEPROM
FEATURES
Precision VCC Power Supply Voltage Monitor
5V, 3.3V and 3V systems
Five threshold voltage options
Additional voltage monitoring
Externally adjustable down to 1.25V
Watchdog timer (CAT1027 only)
Active High or Low Reset
Valid reset guaranteed at VCC = 1V
400kHz I2C Bus
2.7V to 5.5V Operation
Low power CMOS technology
16-Byte Page Write Buffer
supply monitor and reset circuit protects memory and
systems controllers during power up/down and
against brownout conditions. If power supply voltages
are out of tolerance reset signals become active
preventing the system microcontroller, ASIC, or
peripherals from operating.
The CAT1026 features two open drain reset outputs:
one (RESET) drives high and the other (R¯¯E¯S¯E¯T¯)
drives low whenever VCC falls below the threshold.
Reset outputs become inactive typically 200 ms after
the supply voltage exceeds the reset threshold value.
With both active high and low reset signals, interface
to microcontrollers and other ICs is simple. CAT1027
has only a R¯¯E¯S¯E¯T¯ output. In addition, the R¯¯E¯S¯E¯T¯ pin
can be used as an input for push-button manual reset
capability.
Built-in inadvertent write protection
The CAT1026 and CAT1027 provide an auxiliary
1,000,000 Program/Erase cycles
Manual Reset capability
100 year data retention
voltage sensor input, VSENSE, which is used to monitor
a secondwww.DataSheet4U.com system supply. The auxiliary high impe-
dance comparator drives the open drain output, VLOW,
whenever the sense voltage is below 1.25V threshold.
Industrial and extended temperature ranges
8-pin DIP, SOIC, TSSOP, MSOP or TDFN
(3 x 3mm foot-print) packages
TDFN max height is 0.8mm
The CAT1027 is designed with a 1.6 second
watchdog timer circuit that resets a system to a known
state if software or a hardware glitch halts or “hangs”
the system. The CAT1027 features a watchdog timer
interrupt input, WDI.
For Ordering Information details, see page 19.
DESCRIPTION
The CAT1026 and CAT1027 are complete memory
and supervisory solutions for microcontroller-based
systems. A 2k-bit serial EEPROM memory and a
system power supervisor with brown-out protection
are integrated together in low power CMOS techno–
logy. Memory interface is via a 400kHz I2C bus.
The on-chip 2k-bit EEPROM memory features a 16-byte
page. In addition, hardware data protection is provided
by a VCC sense circuit that prevents writes to memory
whenever VCC falls below the reset threshold or until VCC
reaches the reset threshold during power up.
Available packages include 8-pin DIP and surface
mount, 8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin
MSOP packages. The TDFN package thickness is
0.8mm maximum. TDFN footprint is 3 x 3mm.
The CAT1026 and CAT1027 provide a precision VCC
sense circuit with five reset threshold voltage options
that support 5V, 3.3V and 3V systems. The power
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 3010 Rev. L

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CAT1027 equivalent
CAT1026, CAT1027
CAPACITANCE
TA = 25ºC, f = 1.0MHz, VCC = 5V
Symbol
COUT(1)
CIN(1)
Test
Output Capacitance
Input Capacitance
Test Conditions
VOUT = 0V
VIN = 0V
Max
8
6
Units
pF
pF
AC CHARACTERISTICS
VCC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle(2)
Symbol Parameter
Min Max Units
fSCL Clock Frequency
tSP Input Filter Spike Suppression (SDA, SCL)
400 kHz
100 ns
tLOW Clock Low Period
1.3 µs
tHIGH
tR(1)
tF(1)
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
0.6
300
300
µs
ns
ns
tHD; STA
tSU; STA
Start Condition Hold Time
Start Condition Setup Time (for a Repeated Start)
0.6 µs
0.6 µs
tHD; DAT Data Input Hold Time
0 ns
tSU; DAT Data Input Setup Time
100 ns
tSU; STO Stop Condition Setup Time
0.6 µs
tAA SCL Low to Data Out Valid
900 ns
tDH Data Out Hold Time
50 ns
tBUF(1) Time the Bus must be Free Before a New Transmission Can Start
1.3
µs
tWC(3) Write Cycle Time (Byte or Page)
5 ms
Notes:
(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(2) Test Conditions according to “AC Test Conditions” table.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 3010 Rev. L


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Part Details

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