Datenblatt-pdf.com


CAT1024 Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT1024
Beschreibung (CAT1024 / CAT1025) Supervisory Circuits
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 20 Seiten
CAT1024 Datasheet, Funktion
CAT1024, CAT1025
Supervisory Circuits with I2C Serial 2k-bit
CMOS EEPROM and Manual Reset
FEATURES
DESCRIPTION
Precision Power Supply Voltage Monitor
— 5V, 3.3V and 3V systems
— Five threshold voltage options
Active High or Low Reset
— Valid reset guaranteed at VCC = 1V
The CAT1024 and CAT1025 are complete memory
and supervisory solutions for microcontroller-based
systems. A 2k-bit serial EEPROM memory and a
system power supervisor with brown-out protection
are integrated together in low power CMOS techno–
logy. Memory interface is via a 400kHz I2C bus.
400kHz I2C Bus
2.7V to 5.5V Operation
Low power CMOS technology
16-Byte Page Write Buffer
Built-in inadvertent write protection
— WP pin (CAT1025)
The CAT1025 provides a precision VCC sense circuit
and two open drain outputs: one (RESET) drives high
and the other (R¯¯E¯S¯E¯T¯) drives low whenever VCC falls
below the reset threshold voltage. The CAT1025 also
has a Write Protect input (WP). Write operations are
disabled if WP is connected to a logic high.
1,000,000 Program/Erase cycles
Manual Reset Input
100 year data retention
The CAT1024 also provides a precision VCC sense
circuit, but has only a R¯¯E¯S¯E¯T¯ output and does not
have a Write Protect input.
Industrial and extended temperature ranges Thewww.DataSheet4U.com power supply monitor and reset circuit protect
Green packages available with NiPdAu Lead
finished
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 200 ms after the supply
voltage exceeds the reset threshold level. With both
active high and low reset signals, interface to
microcontrollers and other ICs is simple. In addition,
the R¯¯E¯S¯E¯T¯ pin or a separate input, ¯M¯R¯, can be used
For Ordering Information details, see page 19.
as an input for push-button manual reset capability.
The CAT1024/25 memory features a 16-byte page. In
addition, hardware data protection is provided by a
VCC sense circuit that prevents writes to memory
whenever VCC falls below the reset threshold or until
VCC reaches the reset threshold during power up.
Available packages include an 8-pin DIP and a
surface mount 8-pin SO, 8-pin TSSOP, 8-pin TDFN
and 8-pin MSOP packages. The TDFN package thick-
ness is 0.8mm maximum. TDFN footprint is 3x3mm.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 3008 Rev. N






CAT1024 Datasheet, Funktion
CAT1024, CAT1025
RESET CIRCUIT AC CHARACTERISTICS
Symbol
tPURST
tRDP
tGLITCH
MR Glitch
tMRW
tMRD
Parameter
Power-Up Reset Timeout
VTH to RESET Output Delay
VCC Glitch Reject Pulse Width
Manual Reset Glitch Immunity
MR Pulse Width
MR Input to RESET Output Delay
POWER-UP TIMING (5), (6)
Symbol
tPUR
tPUW
Parameter
Power-Up to Read Operation
Power-Up to Write Operation
Test Conditions Min Typ Max Units
Note 2
130 200
270
ms
Note 3
5 µs
Note 4, 5
30 ns
Note 1
100 ns
Note 1
5
µs
Note 1
1 µs
Test Conditions Min Typ Max Units
270 ms
270 ms
AC TEST CONDITIONS
Parameter
Input Pulse Voltages
Input Rise and Fall Times
Input Reference Voltages
Output Reference Voltages
Output Load
Test Conditions
0.2VCC to 0.8VCC
10ns
0.3VCC, 0.7VCC
0.5VCC
Current Source: IOL = 3mA; CL = 100pF
RELIABILITY CHARACTERISTICS
Symbol
NEND(5)
TDR(5)
VZAP(5)
ILTH(5)(7)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Max
Units
Cycles/Byte
Years
Volts
mA
Notes:
(1) Test Conditions according to “AC Test Conditions” table.
(2) Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(3) Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(4) VCC Glitch Reference Voltage = VTHmin; Based on characterization data
(5) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(6) tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.
(7) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to VCC + 1V.
Doc. No. 3008 Rev. N
6 © 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

6 Page









CAT1024 pdf, datenblatt
CAT1024, CAT1025
Acknowledge Polling
Disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host’s write opration, the CAT1024/25 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address for a write operation. If
the device is still busy with the write operation, no
ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can
then proceed with the next read or write operation.
WRITE PROTECTION PIN (WP)
The Write Protection feature (CAT1025 only) allows
the user to protect against inadvertent memory array
programming. If the WP pin is tied to VCC, the entire
memory array is protected and becomes read only.
The CAT1025 will accept both slave and byte addre-
sses, but the memory location accessed is protected
from programming by the device’s failure to send an
acknowledge after the first byte of data is received.
READ OPERATIONS
The READ operation for the CAT1024/25 is initiated in the
same manner as the write operation with one exception,
the R/¯W¯ bit is set to one. Three different READ operations
are possible: Immediate/Current Address READ,
Selective/Random READ and Sequential READ.
Figure 10. Immediate Address Read Timing
BUS ACTIVIT Y:
MASTER
S
T
A
R
T
SDA LINE S
SLAVE
ADDRESS
A
C
K
DATA
S
T
O
P
P
N
O
A
C
K
SCL
89
SDA
8TH BI T
DATA OUT
NO ACK
STOP
Doc. No. 3008 Rev. N
12 © 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

12 Page





SeitenGesamt 20 Seiten
PDF Download[ CAT1024 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
CAT102Precision/ Adjustable Shunt Regulator (600mV Reference)Catalyst Semiconductor
Catalyst Semiconductor
CAT1021(CAT1021 - CAT1023) Supervisory CircuitsCatalyst Semiconductor
Catalyst Semiconductor
CAT1021(CAT1021 - CAT1023) Supervisory CircuitsON Semiconductor
ON Semiconductor
CAT1022(CAT1021 - CAT1023) Supervisory CircuitsCatalyst Semiconductor
Catalyst Semiconductor
CAT1022(CAT1021 - CAT1023) Supervisory CircuitsON Semiconductor
ON Semiconductor

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche