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CAT24FC64 Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT24FC64
Beschreibung 64K-Bit I2C Serial CMOS EEPROM
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 10 Seiten
CAT24FC64 Datasheet, Funktion
CAT24FC64
64K-Bit I2C Serial CMOS EEPROM
FEATURES
I Fast mode I2C bus compatible*
I Industrial and extended
temperature ranges
I Max clock frequency:
I 5 ms max write cycle time
- 400KHz for VCC=2.5V to 5.5V
I Schmitt trigger filtered inputs for noise suppression
I Low power CMOS technology
I 64-byte page write buffer
rtI Self-timed write cycle with auto-clear
I Write protect feature
– entire array protected when WP at VIH
I 1,000,000 program/erase cycles
I 100 year data retention
I 8-pin DIP, 8-pin SOIC (JEDEC), 8-pin SOIC
(EIAJ), 8-pin TSSOP and TDFN packages
DESCRIPTION
aThe CAT24FC64 is a 64K-bit Serial CMOS EEPROM
internally organized as 8,192 words of 8 bits each.
PCatalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24FC64
features a 64-byte page write buffer. The device oper-
ates via the I2C bus serial interface and is available in 8-
pin DIP, SOIC, TSSOP and TDFN packages.
dPIN CONFIGURATION
BLOCK DIAGRAM
eDIP Package (P, L, GL) TDFN Package (RD2, ZD2)
EXTERNAL LOAD
A0
uA1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
tinSOIC Package
(J, W, K, X, GW, GX)
A0 1
A1 2
A2 3
VSS 4
(Top View)
8 VCwCww.DataSheet4U.com
7 WP
6 SCL
5 SDA
VCC
VSS
TSSOP Package (U, Y, GY)
SDA
nA0
A1
oA2
VSS
1
2
3
4
8 VCC A0 1
7 WP A1 2
6 SCL A2
3
5 SDA VSS 4
8 VCC
7 WP
6 SCL
5 SDA WP
DOUT
ACK
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
CONTROL
LOGIC
XDEC
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
512
EEPROM
128 128X512
cPIN FUNCTIONS
isPin Name
Function
A0, A1, A2 Address Inputs
DSDA
Serial Data/Address
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
SCL Serial Clock
WP Write Protect
SCL
STATE COUNTERS
VCC +2.5V to +5.5V Power Supply
VSS Ground
A0 SLAVE
A1 ADDRESS
A2 COMPARATORS
NC No Connect
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1046, Rev. K






CAT24FC64 Datasheet, Funktion
CAT24FC64
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
If the Master transmits more than 64 bytes before sending
the STOP condition, the address counter wraps around,
and previously transmitted data will be overwritten.
WRITE OPERATIONS
When all 64 bytes are received, and the STOP condition
Byte Write
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
In the Byte Write mode, the Master device sends the the CAT24FC64 in a single write cycle.
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
Acknowledge Polling
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24FC64. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
rtmemory location. The CAT24FC64 acknowledges once
more and the Master generates the STOP condition. At
this time, the device begins an internal programming
acycle to nonvolatile memory. While the cycle is in
progress, the device will not respond to any request from
the Master device.
PPage Write
The CAT24FC64 writes up to 64 bytes of data, in a single
dwrite cycle, using the Page Write operation. The page
write operation is initiated in the same manner as the
ebyte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 63 additional bytes. After each byte has
ubeen transmitted, CAT24FC64 will respond with an
acknowledge, and internally increment the six low order
tinaddress bits by one. The high order bits remain un-
changed.
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24FC64 initiates the internal write cycle. ACK poll-
ing can be initiated immediately. This involves issuing
the start condition followed by the slave address for a
write operation. If CAT24FC64 is still busy with the write
operation, no ACK will be returned. If
CAT24FC64 has completed the write operation, an ACK
will be returned and the host can then proceed with the
next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is
protected and becomes read only. The CAT24FC64 will
accept both slave and byte addresses, but the memory
location accessed is protected from programming by the
devices failure to send an acknowledge after the first
byte of data is received.
Figure 6. Byte Write Timing
nS
T
BUS ACTIVITY: A SLAVE
oMASTER R ADDRESS
T
BYTE ADDRESS
A15A8
A7A0
DATA
S
T
O
P
cSDA LINE S
P
is ****=Don't Care Bit
A A AA
C C CC
K K KK
DFigure 7. Page Write Timing
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE S
SLAVE
ADDRESS
BYTE ADDRESS
A15A8
A7A0
***
A
C
K
A
C
K
*=Don't Care Bit
A
C
K
Doc. No. 1046, Rev. K
6
DATA
DATA n
DATA n+63
S
T
O
P
P
A AA A
C CC C
K KK K
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

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