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PDF CAT24FC16 Data sheet ( Hoja de datos )
| Número de pieza | CAT24FC16 | |
| Descripción | 16-kb I2C Serial EEPROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT24FC16
16-kb I2C Serial EEPROM
FEATURES
I 400 kHz (2.5 V) and 100 kHz (1.8 V) I2C bus
compatible
I 1.8 to 5.5 volt operation
I Low power CMOS technology
I 16-byte page write buffer
I Industrial and extended temperature ranges
I Self-timed write cycle with auto-clear
ALOGEN FR
LEA D F REETM
I 1,000,000 program/erase cycles
I 100 year data retention
I 8-pin DIP, 8-pin SOIC, 8-pin TSSOP, 8-pin MSOP
and TDFN packages
- “Green” package option available
I 256 x 8 memory organization
I Hardware write protect
DESCRIPTION
The CAT24FC16 is a 16-kb Serial CMOS EEPROM
internally organized as 2048 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24FC16
features a 16-byte page write buffer. The device operates
via the I2C bus serial interface and is available in 8-pin
DIP, 8-pin SOIC, 8-pin TSSOP, 8-pin MSOP and TDFN
packages.
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package (P, L)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
www.DataSheet4U.com
SOIC Package (J, W)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SDA
START/STOP
LOGIC
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
TSSOP Package (U, Y)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
MSOP Package (R, Z)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
TDFN Package (RD4, ZD4)
VCC 1
WP 2
SCL 3
SDA 4
8 NC
7 NC
6 NC
5 VSS
* Catalyst Semiconductor is licensed by Philips Corporation
to carry the I2C Bus Protocol.
XDEC
E2PROM
WP CONTROL
LOGIC
DATA IN STORAGE
SCL
STATE COUNTERS
HIGH VOLTAGE/
TIMING CONTROL
PIN FUNCTIONS
Pin Name
NC
SDA
SCL
WP
VCC
VSS
Function
No Connect
Serial Data/Address
Serial Clock
Write Protect
1.8 V to 5.5 V Power Supply
Ground
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
1
Doc. No. 1054, Rev. G
1 page  
CAT24FC16
I2C BUS PROTOCOL
The following defines the features of the I2C bus proto-
col:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC16 monitor the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 for the CAT24FC16 (see Fig. 5). The next three
significant bits (A10, A9, A8) are the memory array
address bits. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24FC16 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC16 then performs a Read or a Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24FC16 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
When the CAT24FC16 begins a READ mode, it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT24FC16 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
Figure 5. Slave Address Bits
ACKNOWLEDGE
1 0 1 0 A10 A9 A8 R/W Normal Read and Write
DEVICE ADDRESS
5 Doc No. 1054, Rev. G
5 Page 
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™ DPPs ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Publication #: 1054
Revison:
G
Issue date: 07/27/04
11 Page | ||
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