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PDF CAT24C00 Data sheet ( Hoja de datos )
| Número de pieza | CAT24C00 | |
| Descripción | 128-Bit Serial EEPROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT24C00
128-Bit Serial EEPROM
FEATURES
I 400 kHz I2C bus compatible*
I 1,000,000 Program/erase cycles
I 1.8 to 5.5 volt operation
I 100 year data retention
I Low power CMOS technology
I Self-timed write cycle with auto-clear
I 8-pin DIP, 8-pin SOIC, 8 pin TSSOP and SOT-23
I Industrial and Extended Temperature Ranges
rtDESCRIPTION
The CAT24C00 is a 128-bit Serial CMOS EEPROM
ainternally organized as 16 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces
device power requirements. The device operates via the
I2C bus serial interface and is available in 8-pin DIP,
8-pin SOIC, 8-pin TSSOP and 5-pin SOT-23.
d PPIN CONFIGURATION
BLOCK DIAGRAM
DIP Package (P, L, GL)
eNC
NC
uNC
tinVSS
1
2
3
4
8 VCC
7 NC
6 SCL
5 SDA
SOIC Package (J, W, GW)
NC
NC
NC
VSS
1
2
3
4
EXTERNAL LOAD
8 VCC
7 NCwww.DataSheet4U.com
6 SCL
5 SDA
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
SOT-23 (TP, TB, GTB)
TSSOP Package (U, Y, GY)
SCL
nVSS
oSDA
1
2
3
5 VCC NC
NC
4 NC
NC
VSS
1
2
3
4
SDA
8 VCC
7 NC
6 SCL
5 SDA
START/STOP
LOGIC
CONTROL
LOGIC
XDEC
E2PROM
iscPIN FUNCTIONS
Pin Name
Function
DSDA
Serial Data/Address
DATA IN STORAGE
SCL Serial Clock
NC No Connect
HIGH VOLTAGE/
TIMING CONTROL
VCC 1.8 V to 5.5 V Power Supply
SCL
STATE COUNTERS
VSS Ground
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1027, Rev. O
1 page  
CAT24C00
START Condition
The CAT24C00 responds with an acknowledge after
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24C00 monitors the
SDA and SCL lines and will not respond until this
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
condition is met.
When the CAT24C00 is in a READ mode it transmits 8
STOP Condition
bits of data, releases the SDA line, and monitors the line
for an acknowledge. Once it receives this acknowledge,
A LOW to HIGH transition of SDA when SCL is HIGH
the CAT24C00 will continue to transmit data. If no
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
rtThe bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
aas 1010 for the CAT24C00 (see Fig. 5). The next three
significant bits are "don't care" bits. The last bit of the
Pslave address specifies whether a Read or Write operation
is to be performed. When this bit is set to 1, a Read
operation is selected, and when set to 0, a Write operation
is selected.
dAfter the Master sends a START condition and the slave
eaddress byte, the CAT24C00 monitors the bus and
responds with an acknowledge (on the SDA line) when
uits address matches the transmitted slave address. The
CAT24C00 then performs a Read or Write operation
depending on the state of the R/W bit.
tinAcknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
nAcknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
oFigure 4. Acknowledge Timing
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
WRITE OPERATION
Byte Write
In the Write mode, the Master device sends the START
condition and the slave address information (with the R/
W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends the byte
address that is to be written into the address pointer of
the CAT24C00. After receiving another acknowledge
from the Slave, the Master device transmits the data
byte to be written into the addressed memory location.
The CAT24C00 acknowledges once more and the
Master generates the STOP condition, at which time the
device begins its internal programming cycle to
nonvolatile memory. While this internal cycle is in
progress, the device will not respond to any request
from the Master device.
After a write command, the internal address counter
will continue to point to the same address location
that was just written. If a stop bit is transmitted to the
device at any point in the write sequence before the
entire sequence is complete, then the command will
abort and no data will be written. If more than eight
iscSCL FROM
D MASTER
1
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
5020 FHD F06
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1027, Rev. O
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CAT24C00.PDF ] | |
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