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PDF W83194BG-903 Data sheet ( Hoja de datos )
| Número de pieza | W83194BG-903 | |
| Descripción | STEPLESS VIA PT/PM MAIN CLOCK GENERATOR | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W83194BR-903 & W83194BG-903
STEPLESS VIA PT/PM MAIN CLOCK
GENERATOR
www.DataSheet4U.com
Date: 5/2/2006
Revision: 1.0
1 page  
W83194BR-903/W83194BG-903
1. GENERAL DESCRIPTION
The W83194BR-903 is a Clock Synthesizer for VIA PT880/PM880 chipset. W83194BR-903 provides
all clocks required for high-speed microprocessor and provides step-less frequency programming and
32 different frequencies of CPU, PCI, and AGP clocks setting, support two 25MHz clock outputs, all
clocks are externally selectable with smooth transitions.
The W83194BR-903 provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable
S.S.T. scale to reduce EMI.
The W83194BR-903 also has watchdog timer and reset output pin to support auto-reset when
systems hanging caused by improper frequency setting.
The W83194BR-903 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
2. PRODUCT FEATURES
• 3 0.7V current-mode Differential pairs clock outputs
• 2 2.5V 25MHz clock outputs
• 3 AGP clock outputs
• 10 PCI synchronous clocks
• 1 24_48Mhz clock output for super I/O.
• 1 48 MHz clock output for USB.
• 2 14.318MHz REF clock outputs.
• AGP/PCI clock out supports synchronous and asynchronous mode
• Smooth frequency switch with selections from 100 to 400MHz
• Step-less frequency programming
• I2C 2-Wire serial interface and support byte read/write and block read/write.
• -0.5% and +/- 0.25% center type spread spectrum
• Programmable S.S.T. scale to reduce EMI
• Programmable registers to enable/stop each output and select modes
• Programmable clock outputs Slew rate control and Skew control
• Watch Dog Timer and RESET# output pins
• 48-pin SSOP package
Publication Release Date: May 2006
- 1 - Revision 1.0
5 Page 
W83194BR-903/W83194BG-903
7. I2C CONTROL AND STATUS REGISTERS
7.1 Register 0: Frequency Select (Default = 10h)
BIT NAME
7 SSEL [4]
PWD
DESCRIPTION
0 Frequency selection by software via I2C
6 SSEL [3]
0
5 SSEL [2]
0
4 SSEL [1]
1
3 SSEL [0]
0
2 EN_SSEL
0 Enable software program FS [4:0].
0 = Select frequency by hardware.
1= Select frequency by software I2C - Bit 7~ 3.
1 EN_SPSP
0 Enable Spread Spectrum in the frequency table.
0 = Normal
1 = Spread Spectrum Enabled
0 EN_SAFE_FREQ 0 Enable reload safe frequency when the watchdog is timeout.
0 = reload the FS [4:0] latched pins when watchdog time out.
1 = reload the safe frequency bit defined at Register 5 bit 4~0.
7.2 Register 1: CPU Clock (1 = Enable, 0 = Stopped) (Default: E2h)
BIT PIN NO PWD
DESCRIPTION
7
45,44
1 CPUT_IPT/CPUC_IPT output control.
6
42,41
1 CPUT1 / C1 output control.
5
39,38
1 CPUT0 / C0 output control.
4 - X Power on latched value of FS4 pin. Default: 0 (Read only)
3 - X Power on latched value of FS3 pin. Default: 0 (Read only)
2 - X Power on latched value of FS2 pin. Default: 0 (Read only)
1 - X Power on latched value of FS1 pin. Default: 1 (Read only)
0 - X Power on latched value of FS0 pin. Default: 0 (Read only)
Publication Release Date: May 2006
- 7 - Revision 1.0
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet W83194BG-903.PDF ] | |
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