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AD9549 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9549
Beschreibung Dual Input Network Clock Generator/Synchronizer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9549 Datasheet, Funktion
FEATURES
Flexible reference inputs
Input frequencies: 8 kHz to 750 MHz
Two reference inputs
Loss of reference indicators
Auto and manual holdover modes
Auto and manual switchover modes
Smooth A-to-B phase transition on outputs
Excellent stability in holdover mode
Programmable 16 + 1-bit input divider, R
Differential HSTL clock output
Output frequencies to 750 MHz
Low jitter clock doubler for frequencies of >400 MHz
Single-ended CMOS output for frequencies of <150 MHz
Programmable digital loop filter (<1 Hz to ~100 kHz)
High speed digitally controlled oscillator (DCO) core
Direct digital synthesizer (DDS) with integrated 14-bit DAC
Excellent dynamic performance
Programmable 16 + 1-bit feedback divider, S
Software controlled power-down
Available 64-lead LFCSP package
Dual Input Network Clock
Generator/Synchronizer
AD9549
APPLICATIONS
Network synchronization
Reference clock jitter cleanup
SONET/SDH clocks up to OC-192, including FEC
Stratum 3/3E reference clocks
Wireless base station, controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9549 provides synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9549 generates an output clock, synchronized to one of two
external input references. The external references may contain
significant time jitter, also specified as phase noise. Using a
digitally controlled loop and holdover circuitry, the AD9549
continues to generate a clean (low jitter), valid output clock during
a loss of reference condition, even when both references have failed.
The AD9549 operates over an industrial temperature range of
−40°C to +85°C.
AD9549
BASIC BLOCK DIAGRAM
FDBK_IN
S1 TO S4
REFA_IN
REFB_IN
REFERENCE
MONITORS
AND
SWITCHING
R
DIGITAL PLL
R, S DIVIDERS
HOLDOVER
DAC_OUT
FILTER
CLOCK
OUTPUT
DRIVERS
OUT
OUT_CMOS
SERIAL PORT,
I/O LOGIC
SYSTEM CLOCK
MULTIPLIER
DIGITAL INTERFACE
Figure 1.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.






AD9549 Datasheet, Funktion
Parameter
SYSTEM CLOCK INPUT
Min Typ Max
SYSCLK PLL Bypassed
Input Capacitance
Input Resistance
Internally Generated DC Bias Voltage2
Differential Input Voltage Swing3
SYSCLK PLL Enabled
Input Capacitance
Input Resistance
Internally Generated DC Bias Voltage2
Differential Input Voltage Swing3
Crystal Resonator with SYSCLK PLL Enabled
Motional Resistance
CLOCK OUTPUT DRIVERS
HSTL Output Driver
Differential Output Voltage Swing
2.4
0.93
632
2.4
0.93
632
1080
1.5
2.6
1.17
3
2.6
1.17
9
1280
2.8
1.38
2.8
1.38
100
1480
Common-Mode Output Voltage2
CMOS Output Driver
0.7 0.88 1.06
Output Voltage High (VOH)
Output Voltage Low (VOL)
Output Voltage High (VOH)
Output Voltage Low (VOL)
TOTAL POWER DISSIPATION
All Blocks Running4
Power-Down Mode
2.7
0.4
1.4
0.4
1060
24
1310
70
Digital Power-Down Mode
Default with SYSCLK PLL Enabled
565 713
955
Default with SYSCLK PLL Disabled
945 1115
With REFA or REFB Power-Down
With HSTL Clock Driver Power-Down
With CMOS Clock Driver Power-Down
1 Must be 0 V relative to AVDD3 (Pin 14) and 0 V relative to AVSS (Pin 33, Pin 43).
2 Relative to AVSS (Pin 33, Pin 43).
3 Must be 0 V relative to AVDD (Pin 36) and ≥0 V relative to AVSS (Pin 33, Pin 43).
4 Typical measurement done with only REFA and HSTL output doubler turned off.
1105
1095
1107
AD9549
Unit Test Conditions/Comments
System clock inputs should always be ac-
coupled (both single-ended and differential)
pF
kΩ
V
mV p-p
Single-ended, each pin
Differential
0 dBm into 50 Ω
pF
kΩ
V
mV p-p
Single-ended, each pin
Differential
0 dBm into 50 Ω
Ω 25 MHz, 3.2 mm × 2.5 mm AT cut
mV Output driver static; see Figure 12 for output
swing vs. frequency
V
Output driver static; see Figure 13 and
Figure 14 for output swing vs. frequency
V IOH = 1 mA, (Pin 37) = 3.3 V
V IOL = 1 mA, (Pin 37) = 3.3 V
V IOH = 1 mA, (Pin 37) = 1.8 V
V IOL = 1 mA, (Pin 37) = 1.8 V
mW Worst case over supply, temperature, process
mW Using either the power-down and enable
register (Register 0x0010) or the PWRDOWN pin
mW
mW After reset or power-up with fS = 1 GHz,
S4 = 0, S1 to S3 = 1, fSYSCLK = 25 MHz
mW After reset or power-up with fS = 1 GHz,
S1 to S4 = 1
mW One reference still powered up
mW
mW
Rev. D | Page 5 of 76

6 Page









AD9549 pdf, datenblatt
AD9549
Pin No.
20, 21
22
27
28
31
32
33, 39, 43, 52
34
35
37
38
40
41
48
50
51
56
57
58
59
Input/
Output
O
Pin Type
O Current set
resistor
I Differential
input
I Differential
input
O
I 1.8 V CMOS
O GND
O 1.8 V HSTL
O 1.8 V HSTL
I Power
O 3.3 V CMOS
I Differential
input
I Differential
input
O Current set
resistor
O Differential
output
O Differential
output
I/O 3.3 V CMOS
I/O 3.3 V CMOS
I 3.3 V CMOS
I 3.3 V CMOS
Mnemonic
PFD_VRB,
PFD_VRT
PFD_RSET
SYSCLK
SYSCLKB
LOOP_FILTER
CLKMODESEL
AVSS
OUTB
OUT
AVDD3
OUT_CMOS
FDBK_INB
FDBK_IN
DAC_RSET
DAC_OUT
DAC_OUTB
REFSELECT
HOLDOVER
PWRDOWN
RESET
Description
These pins must be capacitively decoupled. See the Phase Detector Pin
Connections section for details.
Connect a 5 kΩ resistor from this pin to ground (see the Phase Detector Pin
Connections section).
System Clock Input. The system clock input has internal dc biasing and should
always be ac-coupled, except when using a crystal. Single-ended 1.8 V CMOS
can also be used, but it may introduce a spur caused by an input duty cycle
that is not 50%. When using a crystal, tie the CLKMODESEL pin to AVSS, and
connect crystal directly to this pin and Pin 28.
Complementary System Clock. Complementary signal to the input provided
on Pin 27. Use a 0.01 μF capacitor to ground on this pin if the signal provided
on Pin 27 is single-ended.
System Clock Multiplier Loop Filter. When using the frequency multiplier to
drive the system clock, an external loop filter must be constructed and attached to
this pin. This pin should be pulled down to ground with a 1 kΩ resistor when
the system clock PLL is bypassed. See Figure 44 for a diagram of the system
clock PLL loop filter.
Clock Mode Select. Set to GND when connecting a crystal to the system clock
input (Pin 27 and Pin 28). Pull up to 1.8 V when using either an oscillator or an
external clock source. This pin can be left floating when the system clock PLL is
bypassed. (See the SYSCLK Inputs section for details on the use of this pin.)
Analog Ground. Connect to ground.
Complementary HSTL Output. See the Specifications and Primary 1.8 V
Differential HSTL Driver sections for details.
HSTL Output. See the Specifications and Primary 1.8 V Differential HSTL Driver
sections for details.
Analog Supply for CMOS Output Driver. This pin is normally 3.3 V but can be
1.8 V. This pin should be powered even if the CMOS driver is not used. See the
Power Supply Partitioning section for power supply partitioning.
CMOS Output. See the Specifications and the Output Clock Drivers and 2×
Frequency Multiplier sections. This pin is 1.8 V CMOS if Pin 37 is set to 1.8 V.
Complementary Feedback Input. In standard operating mode, this pin is
connected to the filtered DAC_OUTB output. This internally biased input is
typically ac-coupled, and when configured as such, can accept any differential
signal whose single-ended swing is at least 400 mV.
Feedback Input. In standard operating mode, this pin is connected to the
filtered DAC_OUT output.
DAC Output Current Setting Resistor. Connect a resistor (usually 10 kΩ) from
this pin to GND. See the DAC Output section.
DAC Output. This signal should be filtered and sent back on chip through
FDBK_IN input. This pin has an internal 50 Ω pull-down resistor.
Complementary DAC Output. This signal should be filtered and sent back on
chip through FDBK_INB input. This pin has an internal 50 Ω pull-down resistor.
Reference Select Input. In manual mode, the REFSELECT pin operates as a high
impedance input pin; and in automatic mode, it operates as a low impedance
output pin. Logic 0 (low) indicates/selects REFA. Logic 1 (high) indicates/selects
REFB. There is no internal pull-up/pull-down resistor on this pin.
Holdover (Active High). In manual holdover mode, this pin is used to force the
AD9549 into holdover mode. In automatic holdover mode, it indicates
holdover status. There is no internal pull-up/pull-down resistor on this pin.
Power-Down. When this active high pin is asserted, the device becomes
inactive and enters the full power-down state. This pin has an internal 50 kΩ
pull-down resistor.
Chip Reset. When this active high pin is asserted, the chip goes into reset. Note
that on power-up, it is recommended that the user assert a high to low edge
after the power supplies reach a threshold and stabilize. This pin has an
internal 50 kΩ pull-down resistor.
Rev. D | Page 11 of 76

12 Page





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