PDF AD9540 Data sheet ( Hoja de datos )

Número de pieza	AD9540
Descripción	655 MHz Low Jitter Clock Generator
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet 655 MHz Low Jitter Clock Generator AD9540 FEATURES Excellent intrinsic jitter performance 200 MHz phase frequency detector inputs 655 MHz programmable input dividers for the phase frequency detector (÷M, ÷N) {M, N = 1 to 16} (bypassable) Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable) 8 programmable phase/frequency profiles 400 MSPS internal DDS clock speed 48-bit frequency tuning word resolution 14-bit programmable phase offset 1.8 V supply for device operation 3.3 V supply for I/O, CML driver, and charge pump output Software controlled power-down 48-lead LFCSP package Programmable charge pump current (up to 4 mA) Dual-mode PLL lock detect 655 MHz CML-mode PECL-compliant output driver APPLICATIONS Clocking high performance data converters Base station clocking applications Network (SONET/SDH) clocking Gigabit Ethernet (GbE) clocking Instrumentation clocking circuits Agile LO frequency synthesis Automotive radar FM chirp source for radar and scanning systems Test and measurement equipment Acousto-optic device drivers FUNCTIONAL BLOCK DIAGRAM AVDD AGND DVDD DGND CP_VDD CP_RSET REFIN REFIN SYNC_IN/STATUS CLK1 CLK1 SCLK SDI/O SDO CS S2 S1 S0 SYNC, PLL LOCK M DIVIDER N DIVIDER PHASE FREQUENCY DETECTOR CP REF, AMP CHARGE PUMP DIVIDER 1, 2, 4, 8 SERIAL CONTROL PORT TIMING AND CONTROL LOGIC PHASE/ FREQUENCY PROFILES CML CLK DIVCLK 48 14 AD9540 DDS 10 DAC CP_OUT CLK2 CLK2 DRV_RSET OUT0 OUT0 IOUT IOUT Figure 1. DAC_RSET Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet Parameter FIN = 1966.08 MHz, FOUT = 491.52 MHz @ 10 Hz @ 100 Hz @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz >3 MHz FIN = 2488 MHz, FOUT = 622 MHz @ 10 Hz @ 100 Hz @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz ≥3 MHz PHASE FREQUENCY DETECTOR/CHARGE PUMP REFIN Input Input Frequency2 ÷M Set to Divide by at Least 4 ÷M Bypassed Input Voltage Levels Input Capacitance Input Resistance CLK2 Input Input Frequency ÷N Set to Divide by at Least 4 ÷N Bypassed Input Voltage Levels Input Capacitance Input Resistance Charge Pump Source/Sink Maximum Current Charge Pump Source/Sink Accuracy Charge Pump Source/Sink Matching Charge Pump Output Compliance Range3 STATUS Drive Strength PHASE FREQUENCY DETECTOR NOISE FLOOR @ 50 kHz PFD Frequency @ 2 MHz PFD Frequency @ 100 MHz PFD Frequency @ 200 MHz PFD Frequency RF DIVIDER (CLK1 ) INPUT SECTION (÷R) RF Divider Input Range Min 200 200 0.5 1 Input Capacitance (DC) Input Impedance (DC) Input Duty Cycle Input Power/Sensitivity Input Voltage Level 42 −10 200 Typ Max 105 112 122 130 141 144 146 100 108 115 125 135 140 142 Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz AD9540 Test Conditions/Comments RF Divider R = 4 RF Divider R = 4 450 1500 655 200 600 10 MHz MHz mV p-p pF Ω 450 1500 2 655 200 600 10 4 5 2 CP_VDD − 0.5 MHz MHz mV p-p pF Ω mA % % V mA 148 dBc/Hz 133 dBc/Hz 116 dBc/Hz 113 dBc/Hz 2700 3 1500 50 58 +4 1000 MHz pF Ω % dBm mV p-p DDS SYSCLK not to exceed 400 MSPS Single-ended, into a 50 Ω load4 Rev. B \| Page 5 of 32 5 Page Data Sheet Pin No. 31, 35 32 33 36 39 40 41 42 45 46 47 Paddle Mnemonic CP_VDD OUT0 OUT0 CP_OUT REFIN REFIN CLK2 CLK2 CP_RSET DRV_RSET DAC_RSET Exposed Paddle AD9540 Description Charge Pump and CML Driver Supply Pin. 3.3 V analog (clean) supply. CML Driver Complementary Output. CML Driver Output. Charge Pump Output. Phase Frequency Detector Reference Input. Phase Frequency Detector Reference Complementary Input. Phase Frequency Detector Oscillator (Feedback) Complementary Input. Phase Frequency Detector Oscillator (Feedback) Input. Charge Pump Current Set. Program charge pump current with a resistor to AGND. CML Driver Output Current Set. Program CML output current with a resistor to AGND. DAC Output Current Set. Program DAC output current with a resistor to AGND. The exposed paddle on this package is an electrical connection as well as a thermal enhancement. In order for the device to function properly, the paddle must be attached to analog ground. Rev. B \| Page 11 of 32 11 Page

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