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CE5038 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer CE5038
Beschreibung DVB-S2 Advanced Modulation Satellite Tuner
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 41 Seiten
CE5038 Datasheet, Funktion
CE5038
DVB-S2 Advanced Modulation
Satellite Tuner
Data Sheet
Features
• Single-chip L band to zero IF quadrature down
converter compliant with 1-45 Msps DVB-S2
• High dynamic range of -92 dBm to -10 dBm
without RF attenuator or RSSI
• High total composite power handling
• Excellent immunity to adjacent channel
interference through programmable and
autocalibrated channel filters
• Integrated power and forget LO oscillators
• 2 degree integrated phase jitter enables excellent
performance for 8 PSK and 16 QAM applications
• Less than +/- 3° and +/-0.6 dB I/Q quadrature
balance
• Integrated RF loop through for cascaded tuner
applications
• Power saving mode
February 2006
Ordering Information
HGCE5038 882068
WGCE5038 882129
HGCE5038 S L9F8 882067
WGCE5038 S L9FY 882071
40-pin QFN Trays
40-pin QFN* Trays
40-pin QFN Tape & Reel
40-pin QFN* Tape & Reel
*Pb free
Applications
• Advanced modulation DVB-S and DSS satellite
receivers requiring upgrade for DVB-S2,
8 PSK / 16 QAM
www.DataSheet4U.com
Figure 1 - Block Diagram
1
Intel Corporation
D55746-001
Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others. Copyright © 2006 Intel Corporation. All rights reserved.






CE5038 Datasheet, Funktion
CE5038
Data Sheet
List of Figures
Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 3 - Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4 - AGC Control Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5 - Typical First Stage RF AGC Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6 - Variation in IIP2 with AGC Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7 - Variation in IIP3 with AGC Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8 - Variation in NF with Input Amplitude (typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9 - RF Input and Output (bypass) Return Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10 - Normalized Filter Transfer Characteristic (setting 20 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11 - Free Running LO Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12 - Copper Dimensions for Optimum Heat Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13 - Paste Mask for Reduced Paste Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 14 - Typical Oscillator Arrangement with Optional Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 15 - Typical Arrangement for External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5
Intel Corporation

6 Page









CE5038 pdf, datenblatt
Pin Symbol Direction
CE5038
Function
35 PTEST
In
Connected to internal circuit for
monitoring die temperature
Data Sheet
Schematics
PTEST
36 VccLO
37 VccLO
38 LOTEST
+5 v voltage supply for LO
+5 v voltage supply for LO
Bi-directional test port for accessing
IO internal LO
AC couple input.
VccLO
LOTEST
Bias
39 P1
Switching port P1
Out ‘0’ = disabled (high impedance)
‘1’ = enabled
40 CNT
Bonded to paddle. Production continuity
test for paddle soldering
Note: Exposed paddle on rear of package must be connected to GND.
Same configuration as pin 24,
P0
11
Intel Corporation

12 Page





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