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PDF PDSP16510AMA Data sheet ( Hoja de datos )
| Número de pieza | PDSP16510AMA | |
| Descripción | Stand Alone FFT Processor | |
| Fabricantes | Zarlink Semiconductor | |
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PDSP16510A MA
PDSP16510A MA
Stand Alone FFT Processor
Advance Information
The PDSP16510 performs Forward or Inverse Fast
Fourier Transforms on complex or real data sets containing up
to 1024 points. Data and coefficients are each represented by
16 bits, with block floating point arithmetic for increased
dynamic range.
An internal RAM is provided which can hold up to 1024
complex data points. This removes the memory transfer
bottleneck, inherent in building block solutions. Its organisa-
tion allows the PDSP16510 to simultaneously input new data,
transform data stored in the RAM, and to output previous
results. No external buffering is needed for transforms con-
taining up to 256 points, and the PDSP16510 can be directly
connected to an A/D converter to perform continuous trans-
forms. The user can choose to overlap data blocks by either
0%, 50%, or 75%. Inputs and outputs are asynchronous to the
40MHz system clock used for internal operations.
A 1024 point complex transform can be completed in
some 98µs, which is equivalent to throughput rates of 450
million operations per second. Multiple devices can be con-
nected in parallel in order to increase the sampling rate up to
the 40MHz system clock. Six devices are needed to give the
maximum performance with 1024 point transforms.
Either a Hamming or a Blackman-Harris window operator
can be internally applied to the incoming real or complex data.
The latter gives 67dB side lobe attenuation. The operator
values are calculated internally and do not require an external
ROM nor do they incur any time penalty.
The device outputs the real and imaginary components of
the frequency bins. These can be directly connected to the
PDSP16330 in order to produce magnitude and phase values
from the complex data.
Rev
Date
AB
C
MAR 1993 JAN 1997 OCT 1998
D
NOTE
Polyimide is used as an inter-layer dielectric and as
glassivation.
Polymeric material is also used for die attach which according
to the requirement in paragraph 1.2.1.b. (2) precludes
catagorising this device as fully compliant. In every other
respect this device has been manufactured and screened in
full accordance with the requirements of Mil-Std 883 (latest
revision).
CHANGE NOTIFICATION
The change notification requirements of MIL-PRF-38535 will
be implemented on this device type. Known customers will be
notified of any changes since the last buy when ordering
further parts if significant changes have been made.
DS3762
ISSUE 3.0
October 1998
DATA INPUT
3 TERM
WINDOW
OPERATOR
COEFFICIENT
ROM
WORKSPACE
RAM
WORKSPACE
RAM
FOUR
DATA PATHS
OUTPUT
BUFFER
RESULT OUPUT
FEATURES
Fig. 1. Block Diagram
Completely self contained FFT Processor
Internal RAM supports up to1024 complex points
16 bit data and coefficients plus block floating point for
increased dynamic range
450 MIP operation gives 98 microsecond transforma-
tion times for 1024 points
Up to 40MHz sampling rates with A grade multiple
devices.
Internal window operator gives 67dB side lobe
attenuation and needs no external ROM.
132 pin surface mount package
ORDERING INFORMATION
PDSP16510A MA GCPR (Power Ceramic QFP Package
- HIREL LEVEL A Screening)
PDSP16510A MA AC1R (Power Ceramic PGA Package
- HIREL LEVEL A Screening)
1
1 page  
PDSP16510A MA
spaced frequencies are to be detected, and one is of smaller
magnitude than the other. It does, however, reduce the actual
frequency resolution, and the Hamming window may then be
preferable.
Data in and out of the device is represented by 16 bit real
and imaginary components, with 16 bit sine and cosine values
contained in an internal ROM. Conditional scaling, coupled
with word growth through the butterfly data path, gives in-
creased dynamic range. Transforms can be computed with
sample sizes of either 256 or 1024 data points. The 256 point
option can alternatively be used to simultaneously execute
either four 64 point transforms, or sixteen 16 point transforms.
The 16 point mode can only be used with a rectangular
window, and no overlapping of data blocks is possible.
The device can be configured, either, to perform continu-
ous transforms in a real time application, or as slave processor
to a more general purpose signal processing system. In the
continuous mode, with transform sizes of 256 points or less,
it contains three internal control units which simultaneously
allow new data to be loaded, present data to be transformed,
and previous results to be dumped. Additional, external, input/
output buffering is not needed. The internal input buffer also
allows data blocks to be overlapped by either 50% or 75%,
apart from the mode with no overlaps.
When 1024 point transforms are to be calculated, without loss
of incoming data during the transform time, it is necessary to
use an input buffer. This requirement is satisfied by a single
PDSP16540 support device.
In any of the real or complex modes it is possible to obtain
higher performance by connecting devices in parallel. It is then
possible to increase the sampling rate to that of the system
clock used for internal operations.
The mode of operation of the device is controlled by 16
bits in a control register. These are loaded through the
AUX15:0 port when a control signal DEF is active low. This
port is also used to provide the imaginary component of
complex input data, and, if complex transforms are to be
performed, an external tristate buffer will be needed to isolate
the control information. This should only be enabled when
DEF is active. DEF is also used to initiliase the internal
circuitry, and can be a simple power on reset if control
parameters need not be subsequently changed.
DATA PRECISION
During each pass of a radix-4 fast Fourier transform it is
possible for either component of a particular result to grow by
a factor of up to four in the first pass, and 5.242 in subsequent
passes. This is between two and three bits in each pass and
the data path must allow for this word growth to avoid any
possibility of overflow. At the end of the data path the word is
again reduced to 16 bits by discarding least significant bits..
Any un-necessary word growth to prevent overflow thus
results in loss of arithmetic precision, and has a detrimental
effect on the dynamic range achievable.
In practice these large word growths only occur when
bipolar complex square waves are transformed, and even
then will not occur on every pass. The PDSP16510 compro-
mises by allowing a 2 bit word growth during the butterfly
calculation in the first pass. This is equivalent to ignoring the
most significant bit of the 19 bit final result ,which is assumed
to be an extra sign bit, and then selecting the next 16 bits for
INPUT
SELECT
RAM
SIN / COS
ROM
16
Shift left until largest point
has one sign bit.
16
MULTIPLIER
S S 29 - 14 13 - 0
"1"
18
16
CR
BIT3
FIRST ADDER
19Bit Result
18 - 1 0
REGISTER FILE
SECOND ADDER
19Bit Result
18 - 1 0
REGISTER FILE
THIRD ADDER
19Bit Result
18 - 3
17 - 2
SELECT
Fig. 3 One of Four Data Paths
storage. In subsequent passes a Control Register Bit allows
the user to continue to select these 16 bits, or instead to use
the 16 most significant bits. The latter option is equivalent to
a 3 bit word growth. The 2 or 3 bit word growth option applies
to ALL subsequent passes and is not a per pass option.
If the 2 bit option is selected there is a possibility of
overflow occurring in one of the passes. The prediction of
overflow is mathematically difficult, and only occurs with
specific complex square waves. Scaling down the inputs
cannot be guaranteed to prevent overflow because of the
5
5 Page 
PDSP16510A MA
AUX
PDSP16510
DIN
O/P
S3:0
HOST
SYSTEM
REAL
ONLY
PARAMETERS POWER
ON RESET
+5V GND
MD5 MD4:0 RES
PDSP 16540
BUCKET
BUFFER
WS RS DAV
GND
AUX
PDSP16510
D
I
R
SYSTEM
CLOCK
Fig. 7. Host Controlled System
GENERAL DUMP CONSIDERATIONS
The tri-state drivers on the output buses are only enabled
when both DAV and DEN are active. When DEN is tied
permanently, low the output bus will start to become valid from
the DOS edge which also generates the DAV output. The next
DOS edge can then be used to transfer the first output to the
next device. When DEN is driven low in response to the DAV
output, the outputs start to become valid when DEN goes low.
The Scale Tag outputs become valid at the same time as data,
and when enabled will continue to indicate the correct value
until all frequency bins have been dumped. If at any time
during the dump operation DEN goes in- active, then both the
data and scale tag outputs will go high impedance after the
delay shown in Table 3.
Valid transformed data is actually available within the
device from DAV going active until INEN again goes active,
and a new set of data is loaded. The output tristate drivers,
however, normally go high impedance when DAV goes in-
active once a dump operation has been completed. In order to
support systems in which it may be necessary to read the
transformed data more than once, a Control Register Bit is
provided which keeps the DAV output active until a further
INEN edge is received. The user must then keep track of how
many outputs have been dumped before INEN is generated to
start a new load operation.
The DAV output can be delayed by an amount equivalent
to the pipeline delay through the PDSP16330. This option is
invoked by setting a control bit, and allows DAV to indicate that
polar data is available at the output of the PDSP16330. When
the option is used the tri-state outputs will be enabled when
data is actually available and DEN is active, and not when DAV
eventually goes active.
Two Control Register Bits allow a range of dump size
options to be supported. In some applications the results of
interest may only lie in the lower 25 or 50% of the frequency
bins, the sampling rate having been chosen to prevent
aliasing, and the transform size having been selected to give
the required frequency resolution. In other systems it is only
necessary to output the second half of a given sized transform.
This is useful when filtering is to be performed in the frequency
domain using Overlap /Discard Fast Convolutions. With this
method FIR filters with N taps can be implemented in the
frequency domain using 50% overlapped transforms on 2N
samples. After multiplication in the frequency domain with the
SAMPLE
CLOCK
SYSTEM
CLOCK
Figure 8. 1024 Point Real Transforms
required frequency response, the inverse transform is per-
formed and the first half of each output is discarded. Since only
half the results are dumped, the dump clock need not be twice
the rate of the clock used to load data.
FULL CO - PROCESSOR OPERATION
A single device can be configured as a co-processor to a
host system in which both the loading and dumping of data is
under the control of the host. Such a system is shown in Figure
7, in which DEN is a host provided enable for host read
operations, and INEN is an enable for host write operations.
DIS and DOS are host data strobes.
The host loads a block of data into the PDSP16510, using
DIS enabled by INEN, which is then automatically trans-
formed. The DAV output provides a flag indicating that the
transform is complete, and results are then read by the host
using DOS enabled by DEN. A new set of inputs is not
normally loaded until the previous results are complete. If,
however, 1024 point transforms are not to be performed,
loading new data could coincide with dumping previous re-
sults. This, however, would require a host system with sepa-
rate input and output buses, and which also allowed coinci-
dent transfers. As discussed previously, transferring results
must take no longer than loading new data to prevent corrup-
tion of the outputs.
In the system illustrated by Figure 7, the host also controls
the mode of operation of the FFT processor. The DEF signal
is produced from an address decode, and the control parame-
ters are loaded from the host bus by connecting the AUX
inputs to the data outputs.
REAL ONLY TRANSFORMS WITH A SINGLE DEVICE
In the simplest case real transforms can, of course, be
computed by forcing zero levels on the imaginary input pins.
The device can, however, be configured to internally perform
two simultaneous real transforms instead of a single complex
transform. The block floating point logic will then use data from
both blocks when it determines the number of shifts to be
applied. This dual transform technique is used to increase the
maximum permissible sampling rates, but since an additional
data pass is required in order to un-scramble the transformed
data, the actual performance is not quite double that possible
11
11 Page | ||
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| PDF Descargar | [ Datasheet PDSP16510AMA.PDF ] | |
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