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PDF PDSP16488AMA Data sheet ( Hoja de datos )
| Número de pieza | PDSP16488AMA | |
| Descripción | Single Chip 2D Convolver | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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PDSP16488A MA
PDSP16488A MA
Single Chip 2D Convolver with Integral Line Delays
Supersedes January 1997 version, DS3742 - 3.1
DS3742 - 5.0 November 2000
The PDSP16488A is a fully integrated, application spe-
cific, image processing device. It performs a two dimensional
convolution between the pixels within a video window and a
set of stored coefficients. An internal multiplier accumulator
array can be multi-cycled at double or quadruple the pixel
clock rate. This then gives the window size options listed in
Table 1.
An internal 32k bit RAM can be configured to provide
either four or eight line delays. The length of each delay can
be programmed to the users requirement, up to a maximum of
1024 pixels per line. The line delays are arranged in two
groups,which may be internally connected in series or may be
configured to accept separate pixel inputs. This allows inter-
laced video or frame to frame operations to be supported.
The 8 bit coefficients are also stored internally and can
be downloaded from a host computer or from an EPROM. No
additional logic is required to support the EPROM and a single
device can support up to 16 convolvers.
The PDSP16488A contains an expansion adder and
delay network which allows several devices to be cascaded.
Convolvers with larger windows can then be fabricated as
shown in Table 2.
Intermediate 32 bit precision is provided to avoid any
danger of overflow, but the final result will not normally occupy
all bits. The PDSP16488A thus provides a multiplier in the
output path, which allows the user to align the result to the
most significant end of the 32 bit word.
Data Window Size Max Pixel Line
Size Width X Depth
Rate Delays
84
88
88
16 4
16 8
4 40MHz 4x1024
4 20MHz 4x1024
8 10MHz 8x512
4 20MHz 4x512
4 10MHz 4x512
Table 1 Single Device Configurations
Max Pixel Pixel
Window size
Rate
Size 3x3 5x5 7x7 9x9 11x11 15x15 23x23
10MHz
8 11 1444
9
10MHz 16 1 2 2 - - - -
20MHz
8 12 2668
-
20MHz 16 1 4 4 - - - -
40MHz 8 1 4 * 4 * - - - -
40MHz 16 2 - - - - - -
* Maximum rate is limited to 30 MHz by line store expansion delays
Table 2 Devices needed to implement typical window sizes
FEATURES
I The PDSP16488A is a fully compatible replacement
for the PDSP16488
I 8 or 16 bit pixels with rates up to 40 MHz
I Window sizes up to 8 x 8 with a single device
I Eight internal line delays
I Supports interlace and frame to frame operations
I Coefficients supplied from an EPROM or remote host
I Expandable in both X and Y for larger windows
I Gain control and pixel output manipulation
I 132 pin QFP
Rev
Date
AB C
MAR 1993 JUL 1996 JAN1997
D
NOTE
Polyimide is used as an inter-layer dielectric and as
glassivation.
Polymeric material is also used for die attach which according
to the requirement in paragraph 1.2.1.b. (2) precludes
catagorising this device as fully compliant. In every other
respect this device has been manufactured and screened in full
accordance with the requirements of Mil-Std 883 (latest revi-
sion).
CHANGE NOTIFICATION
The change notification requirements of MIL-PRF-38535 will
be implemented on this device type. Known customers will be
notified of any changes since the last buy when ordering further
parts if significant changes have been made.
PIXEL
CLOCK
GENERATOR
SYNC
EXTRACT
A/D
CONVERTER
COMPOSITE
OPTIONAL
FIELD
STORE
EPROM
ADDR DATA
POWER ON
RESET
CLK
SYNC
BYPASS
RES
PDSP
DATA
IN
16488A
CONVOLVER
DELAYED
SYNC
OUTPUT
DATA
AUX
DATA
Fig. 1 Typical , Stand Alone, Real Time System
1
1 page  
LINE N-1
3 X 3 WINDOW
C4 C5 C6
LINE N C8 C9 C10
LINE N+1
C0 C1 C2
5 X 5 WINDOW
LINE N-2 C48 C49 C50 C51 C52
LINE N-1 C8 C9 C10 C11 C12
LINE N C40 C41 C42 C43 C44
LINE N+1
C0
C1 C2 C3 C4
LINE N+2 C32 C33 C34 C35 C36
PDSP16488A MA
IP7:0
FIELD
DELAY
VIDEO
LINE N+2
1024
ODD
FIELD
L7:0
1024
1024
N+1
N-1
4X4
OR
8X4
N ARRAY
Output is shifted
by 1 line in
every field
1024
IP7:0
FIELD
DELAY
512
ODD N+1
FIELD
512
N-1
512
VIDEO
LINE N+2
L7:0
*Delay is By-Passed
[REG B,BIT 7 IS SET]
512
* Output is shifted
512
8X8
ARRAY
by 1 line in
N+2 every field
512
N
512
N-2
512
LINE N-3
LINE N-2
LINE N-1
LINE N
LINE N+1
LINE N+2
LINE N+3
LINE N+4
8 X 8 WINDOW
C24 C25 C26 C27 C28 C29 C30 C31
C56 C57 C58 C59 C60 C61 C62 C63
C16 C17 C18 C19 C20 C21 C22 C23
FIELD
DELAY
IP7:0
ODD
FIELD
512
512
512
C48 C49 C50 C51
C8 C9
C10 C11
C40 C41 C42 C43
C0 C1 C2 C3
C32 C33 C34 C35
C52 C53 C54 C55
C12 C13 C14 C15
C44 C45 C46 C47
C4 C5 C6
C7
C36 C37 C38 C39
VIDEO
LINE N+4
L7:0
*Delay is By-Passed
[REG B,BIT 7 IS SET]
512
512
512
512
512
N+3
N+1
N-1
N-3
* 8X8
N+4 ARRAY
N+2
N
N-2
Output is shifted
by 2 lines in
every field
Figure 3. Line Delay Allocations in Single Device Interlaced Systems
5
5 Page 
LOADING REGISTERS FROM A HOST CPU
The expansion data inputs [X14:0] on a single or
master device are connected to the host bus to provide
address and data for the internal registers. In a multiple device
system the remaining devices receive addresses and data
which have been passed through the expansion connection
between earlier devices in the cascade chain. Each device
needs an individual chip enable plus a global data strobe,
read/write line, and PROG signal from the host.
Registers are individually addressed and can be
loaded in any sequence once the global PROG signal has
been produced by the host. The latter would normally be
produced from an address decode encompassing all the
necessary device addresses.
If a self timed system is to be implemented, a timing
strobe must be passed down the expansion chain through the
PC1/PC0 connections. The PC0 output from the final device
is used as a host REPLY signal, and indicates that the last
device has received data after the propogation delay of
previous devices. The timing strobe is produced in the
MASTER device from the host data strobe, and will appear on
the PC0 output. This feature allows the user to cascade any
number of devices without knowing the propogation delay
through each device. The timing information for this mode of
operation is given in Figure 8.
The host can also read the data contained in the
internal registers. The required device is selected using chip
enable with the R/W line indicating a read operation. Single
device systems output the data read on X7:0, but in multiple
device systems data is read from the D7:0 outputs on the final
device in the chain. These must be connected back to the host
data bus through three-state drivers. When earlier devices in
the chain are addressed, the register contents are transferred
through the expansion connections down to the final device.
In the self timed configuration the data will be valid when the
REPLY goes active, as shown in Figure 8.
If the REPLY signal is not to be used , the PC0/PC1
connections are not necessary, and the host data strobe for a
write operation must be wide enough to allow for the worst
case propogation delay through all the devices ( TDEL ). If the
data or address from the host does not meet the set up time
given in Fugure 8, the width of the data strobe can be simply
extended to compensate for the additional delay. When read-
ing data the access time required is: TACC + ( N - 1 ).TDEL
using the maximum times obtained from Figure 8.
HOST CONTROL LINES
X7:0
8 bit data bus. In a single device system this bus is
bi-directional; in other configurations it is an input.
Only a SINGLE or MASTER device is connected
directly to the host. Other devices receive data from
the output of the previous device in the chain.
X14:8
7 bit address bus which is used to identify one of
the 73 internal registers. Connected in the same
manner as X7:0.
X15 X15 must be open circuit on the MASTER device
PDSP16488A MA
PC0 An input from the previous PC1 output in a multiple
device chain. Not needed on a SINGLE device or
if the self timed feature is not used.
PC1 Reply to the host from a SINGLE device or from the
last device in a cascade chain. It indicates that the
write strobe can be terminated. Connected to PC0
input of the next device at intermediate points in the
chain if the self timed feature is used.
R/W
Read/Not Write line from the host CPU which is
connected to all devices in the system.
CE An active low enable which is normally produced
from a global address decode for the particular
device. This must encompass all internal register
addresses.
DS An active low host data strobe which is connected
to all devices. in the system.
PROG
An active low global signal, produced by the host,
which is connected to all devices in the system.
Together with a unique chip enable for every de-
vice, it allows the internal registers to be updated
or examined by the host. PROG and CE should be
tied together in a single device system.
LOADING REGISTERS FROM AN EPROM
In the EPROM supported mode, one device has to
assume the role of a host computer. If more than one device
is present, this must be the first component in the chain,
which must have its MASTER pin tied low.
The MASTER device contains internal address count-
ers which allow the registers in up to 16 cascaded devices to
be specified. It also generates the PROG signal and a data
strobe on the pins which were previously inputs. These
outputs must be connected to the other devices in the system,
which still use them as inputs. The R/W input should be tied
low on all devices.
The width of the data strobe is determined by the
feedback connection from the PC1 output on the last device
to the PC0 input on the MASTER. The PC0/PC1 connections
must be made between devices in a multiple device system;
in a single device system the connection is made internally.
The available EPROM access time is determined by
an internal oscillator and does not require the pixel clock to be
present during the programming sequence. Any pixel clock re-
synchronization in a real time system will thus not effect the
coefficient load operation. The relevent EPROM timing infor-
mation is shown in figure 9.
The load procedure will commence after reset has
gone from active to in-active, and will be indicated by the
PROG output going active. The data from 73 EPROM loca-
tions will be loaded into the internal registers using addresses
corresponding to those in Table 3. Within a particular page of
128 EPROM locations, the first nine locations supply control
register information, and the top 64 supply coefficients. The
middle 55 locations are not used. If the window size is 8 x 4,
the top 32 locations will also contain redundant data, and if
the size is 4 x 4 the top 48 will be redundant.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PDSP16488AMA.PDF ] | |
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