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PDSP16318MC Schematic ( PDF Datasheet ) - Zarlink Semiconductor

Teilenummer PDSP16318MC
Beschreibung Complex Accumulator
Hersteller Zarlink Semiconductor
Logo Zarlink Semiconductor Logo 




Gesamt 8 Seiten
PDSP16318MC Datasheet, Funktion
www.DataSheet4U.com
PDSP16318 MC
PDSP16318 MC
Complex Accumulator
DS3761
ISSUE 2.1
November 1998
The PDSP16318 contains two independent 20-bit Adder/
Subtractors combined with accumulator registers and shift
structures. The four port architecture permits full 10MHz
throughout in FFT and filter applications.
Two PDSP16318s combined with a single PDSP16112A
Complex Multiplier provide a complete arithmetic solution for
a Radix 2 DIT FFT Butterfly. A new complex Butterfly result
can be generated every 100ns allowing 1k complex FTT's to
to be executed in 512µs.
FEATURES
s Full 10MHz Throughout in FFT Applications
s Four Independent 16-bit I/O Ports
s 20-bit Addition or Accumulation
s Fully Compatible with PDSP16112 Complex Multiplier
s On Chip Shift Structures for Result Scaling
s Overflow Detection
s Independent Three-State Outputs and Clock
Enables for 2 Port 10MHz Operation
s 1.4 micron CMOS
s 500mW Maximum Power Dissipation
s 100 pin ceramic QFP
ORDERING INFORMATION
PDSP16318/MC/GC1R (Ceramic QFP Package -
MIL STD 883 Screening)
GC100
Fig.1 Pin connections
Rev
Date
AB
MAR 1993 NOV 1998
C
D
NOTE
Polyimide is used as an inter-layer dielectric and as
glassivation.
A REG
DELAY
B
SHIFT
REG
C
A
B REG
A
SHIFT
REG
D
B
Fig.2 PDSP16318 simplified block diagram
1






PDSP16318MC Datasheet, Funktion
PDSP16318 MC
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb (Military) =-55°C to +125°C, VCC = 5.0V ± 10%, GND = 0V
STATIC CHARACTERISTICS
Characteristic
Symbol
Min.
Value
Typ.
Units Sub
Max.
group
Conditions
* Output high voltage
* Output low voltage
* Input high voltage
* Input low voltage
* Input leakage current
* Output leakage current
† Output SC current
† Input capacitance
V
OH
VOL
VIH
V
IL
V
IH
VI IL
IL
loz
IOS
C
IN
SWITCHING CHARACTERISTICS
2.4
-
2.0
-
Vdd - 1
-
-10
-50
20
-
Characteristic
* Clock period
† Clock High Time
† Clock Low Time
† A15:0, B15:0 setup to clock rising edge
† A15:0, B15:0 hold after clock rising edge
† MS, S2:0, ASI setup to clock rising edge
† DEL, ASR, CLR setup to clock rising edge
† DEL, ASR, CLR, MS, S2:0, ASI hold after
clock rising edge
CEA, CEB setup to clock falling edge
CEA, CEB hold after clock falling edge
† Clock rising edge to OVR, C15:0, D15:0
OEC/OED low to C15:0/D15:0 high data valid
OEC/OED low to C15:0/D15:0 low data valid
OEC/OED high to C15:0/D15:0 high impedance
† Vcc current
- V 1, 2, 3 IOH = 3.2mA
0.4 V 1, 2, 3 lOL=-3.2mA
- V 1, 2, 3
0.8 V 1, 2, 3
- V 1, 2, 3 CLK, CEA, CEB, OEC, OED
0.5 V 1, 2, 3 CLK, CEA, CEB, OEC, OED
+10
µA
1, 2, 3
GND < V <V
IN CC
- +50 µA 1, 2, 3 GND <VIN < VCC
- 200 mA
Vcc = Max
9 - pF
Value
Military
PDSP16318
Min. Max.
Units
100 -
20 -
20 -
8-
2-
10 -
8-
2-
ns
ns
ns
ns
ns
ns
ns
ns
2 - ns
8 - ns
5 40 ns
- 40 ns
- 40 ns
- 40 ns
- 70 mA
Sub
group
9, 10, 11
Conditions
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
VCC = max,
TTL input levels
Outputs unloaded,
fCLK = max
† Vcc current
- 30 mA
All parameters marked * are tested during production.
All parameters marked † are guaranteed by design and characterisation.
NOTES
1. LSTTL is equivalent to IOH = 20 microamps, IOL = -0.4mA
2. Current is defined as negative into the device
3. CMOS input levels are defined as:
V = 0.5V
IL
VIH = VDD - 0.5V
VCC = max,
CMOS input levels
Outputs unloaded,
fCLK = max
6

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