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PDSP16116MC Schematic ( PDF Datasheet ) - Zarlink Semiconductor

Teilenummer PDSP16116MC
Beschreibung 16 by 16 Bit Complex Multiplier
Hersteller Zarlink Semiconductor
Logo Zarlink Semiconductor Logo 




Gesamt 18 Seiten
PDSP16116MC Datasheet, Funktion
www.DataSheet4U.com
PDSP1P6D1S1P166/1A16//AM/MCC
16 by 16 Bit Complex Multiplier
The PDSP16116A will multiply two complex (16 + 16) bit
words every 50ns and can be configured to output the
complete complex (32 + 32) bit result within a single cycle. The
data format is fractional two's complement.
The PDSP16116/A contains four 16 x 16 Array Multipliers,
two 32 bit Adder/Subtractors and all the control logic required
to support Block Floating Point Arithmetic as used in FFT
applications. In combination with a PDSP16318, the
PDSP16116A forms a two chip 10MHz Complex Multiplier
Accumulator with 20 bit accumulator registers and output
shifters. The PDSP16116 in combination with two
PDSP16318s and two PDSP1601s forms a complete 10MHz
Radix 2 DIT FFT Butterfly solution which fully supports Block
Floating Point Arithmetic. The PDSP16116/A has an
extremely high throughput that is suited to recursive
algorithms as all calculations are performed with a single
pipeline delay (two cycle fall-through).
FEATURES
s Complex Number (16 + 16) X (16 + 16) Multiplication
s Full 32 bit Result
s 20MHz Clock Rate
s Block Floating Point FFT Butterfly Support
s -1 times -1 Trap
s Two's Complement Fractional Arithmetic
s TTL Compatible I/O
s Complex Conjugation
s 2 Cycle Fall Through
s 144 pin PGA or QFP packages
APPLICATION
s Fast Fourier Transforms
s Digital Filtering
s Radar and Sonar Processing
s Instrumentation
s Image Processing
ASSOCIATED PRODUCTS
PDSP16318/A
PDSP16112/A
PDSP16330/A
PDSP1601/A
PDSP16350
PDSP16256
PDSP16510
Complex Accumulator
(16 + 16) X (12 + 12) Complex Multiplier
Pythagoras Processor
ALU and Barrel Shifter
Precision Digital Modulator
Programmable FIR Filter
Single Chip FFT Processor
DS3858
ISSUE 3.0
June 2000
Ordering Information
PDSP16116 MC GC1R 10MHz MIL-883 screened -
ceramic QFP
PDSP16116 MC AC1R 10MHz MIL-883 screened -
PGA package
PDSP16116A MC GC1R 20MHz MIL-883 screened -
ceramic QFP
PDSP16116A MC AC1R20MHz MIL-883 screened -
PGA package
XR
REG
XI
REG
YR
REG
YI
REG
MULT
MULT
MULT
MULT
REG
REG
REG
REG
+/- +/-
SHIFT
SHIFT
REG
REG
PR PI
Fig.1 Simplified Block Diagram
CHANGE NOTIFICATION
The change notification requirements of MIL-M-38510 will be
implemented on this device type. Known customers will be
notified of any changes since last buy when ordering further
parts if significant changes have been made.
Rev
Date
AB C
JULY 1993 OCT 1998 JUN 2000
D
1






PDSP16116MC Datasheet, Funktion
PDSP16116/A/MC
NORMAL MODE OPERATION
When the MBFP mode select input is held low the ‘Normal’
mode of operation is selected. This mode supports all
Complex Multiply operations that do not require Block Floating
Point arithmetic.
Multiplier Satge
Complex two's complement fractional data is loaded into
the X and Y input registers via the X and Y Ports on the rising
edge of CLK. The Real and Imaginary components of the
fractional data are each assumed to have the following format
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEIGHTING
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15
S2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Where S = sign bit which has an effective weighting -20
The value of the 16 bit two’s complement word is
Value = (-1xS)+(bit14x2-1)+(bit13x2-2)+(bit12x2-3). . .
The X & Y port registers are individually enabled by the
CEX & CEY signals respectvely. If the registers are required
to be permanently enabled, then these signals may be tied to
ground. On each clock cycle the contents of the input registers
are passed to the four multipliers to start a new Complex
Multiply operation. Each Complex Multiply operation requires
four partial products (Xr x Yr), (Xr x Yi), (Xi x Yr), (Xi x Yi), all
of which are calculated in parallel by the four 16 x 16
Multipliers. Only one clock cycle is required to complete the
multiply stage before the Mutliplier results are loaded into the
Multiplier output registers for passing on to the Adder/
Subtractors in the next cycle. Each multiplier produces a 31
bit result with the duplicate sign bit eliminated. The format of
the output data from the Multipliers is
BIT NUMBER 30 29 28 27 26 25 24 . . . 7 6 5 4 3 2 1 0
WEIGHTING
-1 -2
-3 -4
-5 -6
-23 -24 -25 -26 -27 -28 -29 -30
S 2 2 2 2 2 2 ... 2 2 2 2 2 2 2 2
The effective weighting of the sign bit is -20
Result Correction
Due to the nature of the fraction twos complement
representation it is possible to represent -1 exactly but not 1.
With conventional multipliers this causes a problem when -1
is multiplied by -1 as the multiplier produces an incorrect
result. The PDSP16116 includes a trap to ensure that the
most positive number (value = 1.2-30), (hex = 7FFFFFFFF) is
subsituted for the incorrect result. The multiplier result is
therefore always a (correct) fractional value.
Complex Conjugation
Either the X or Y input data may be complex conjugated by
asserting the CONX or CONY signals respectively. Asserting
either of these signals has the effect of inverting (multiplying
by -1) the imaginary component of the respective input. Table
3 shows the effect of CONX and CONY on the X and Y inputs.
FUNCTION OPERATION
CONX CONY
XxY
X x Conj Y
Conj X x Y
Invalid
(XR+XI)x(YR+YI)
(XR+XI)x(YR-YI)
(XR-XI)x(YR+YI)
Invalid
low
high
low
high
Table 3 Conjugate Functions
Adder / Subtractor Stage
low
low
high
high
The 31 bit Real and Imaginary results from the Multipliers
are passed to two 32 bit Adder/Subtractors. The Adder
calculates the imaginary result ((Xr x Yi) + (Xi x Yr)) and the
Subtractor calculates the Real result ((Xr x Yr) = (Xi x Yi)).
Each Adder/Subtractor produces a 32 bit result with the
following format.
BIT NUMBER 31 30 29 28 27 26 . . . 8 7 6 5 4 3 2 1 0
WEIGHTING
0 -1 -2 -3 -4
-22 -23 -24 -25 -26 -27 -28 -29 -30
S 2 2 2 2 2 ... 2 2 2 2 2 2 2 2 2
The effective weighting of the sign bit is -21
Rounding
The ROUND control when asserted rounds the most
significant 16 bits of the full 32 bit result from the Adder/
Subtractor. If the ROUND signal is active (High), then bit 16
is set to a one, rounding the most significant 16 bits of the
Adder/Subractor result. (The least siginificant 16 bits are
unaffected). Inserting a one ensures that the rounding error
is never greater than 1LSB, and that no DC bias is introduced
as a result of the rounding processes.
The format of the Rounded result is;
BIT NUMBER 31 30 29 28 27 . . . 18 17 16 15 14 13 . . . 2 1 0
WEIGHTING
0 -1 -2 -3
-12 -13 -14 -15 16 -17
-28 -29 -30
S 2 2 2 2 ... 2 2 2 2 2 2 ... 2 2 2
ROUNDED VALUE
LBS's
The effective weighting of the sign is -21
Shifter
Each of the two Adder/Subtractors are followed by Shifters
controlled via the WTB control input. These shifters can each
apply four different shifts, however the same shift is applied to
both real and imaginary components. The four shift options
are:
i) WTB1:0 = 11 Shift complex product one place to the left
giving a shifter output format:
BIT NUMBER 31 30 29 28 27 26 25 . . . 7 6 5 4 3 2 1 0
WEIGHTING
-1 -2 -3 -4 -5 -6
-24 -25 -26 -27 -28 -29 -30 -31
S 2 2 2 2 2 2 ... 2 2 2 2 2 2 2 2
The effective weighting of the sign bit is -20
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PDSP16116MC pdf, datenblatt
PDSP16116/A/MC
AR SOBFP
AR15:13
EOPSS
BR BI WR WI
A XR XI YR YI
WTA WTB
AI15:13
AI
A
PDSP1601/A
SFTA
C
PDSP16116/A
PR PI
PDSP1601/A
SFTA
C
DAR
DAI
AB
PDSP16318/A
SFTR
CD
BA
PDSP16318/A
SFTR
CD
A'R A'I
WTOUT
GWR
B'R B'I
Figure 5 - FFT Butterfly Processor
At the end of each constituent pass of the FFT, the
positions of the binary point supported may change to reflect
the trend of data increase or decreases in magnitude. Hence,
in the pass following that of the above example, the four
positions of binary point supported may be change to:
XX.XXXXXXXXXXXX
XXX.XXXXXXXXXXX
XXXX.XXXXXXXXXX
XXXXX.XXXXXXXXX
word tag = 00
word tag = 01
word tag = 10
word tag = 11
This variation in the range of binary points supported from
pass to pass (i.e. the movement of the binary point relative to
its position in the original data) is recorded in the GWR.
Thus we can determine the position of the binary point
relative to its initial position by modifying the value of GWR by
WTOUT for a given word as shown in Table 6.
As an example, if GWR=01001 and WTOUT=10 then the
binary point has moved 10 places to the right of its original
position.
12

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