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PDSP1601A Schematic ( PDF Datasheet ) - Zarlink Semiconductor

Teilenummer PDSP1601A
Beschreibung ALU and Barrel Shifter
Hersteller Zarlink Semiconductor
Logo Zarlink Semiconductor Logo 




Gesamt 16 Seiten
PDSP1601A Datasheet, Funktion
www.DataSheet4U.com
PDSP1601/PDSP1601A
PDSP1601/PDSP1601A
ALU and Barrel Shifter
DS3705
The PDSP1601 is a high performance 16-bit arithmetic
logic unit with an independent on-chip 16-bit barrel shifter.
The PDSP1601A has two operating modes giving 20MHz or
10MHz register-to-register transfer rates.
The PDSP1601 supports Multicycle multiprecision
operation. This allows a single device to operate at 20MHz for
16-bit fields, 10MHz for 32-bit fields and 5MHz for 64-bit fields.
The PDSP1601 can also be cascaded to produce wider words
at the 20MHz rate using the Carry Out and Carry In pins. The
Barrel Shifter is also capable of extension, for example the
PDSP1601 can used to select a 16-bit field from a 32-bit input
in 100ns.
ISSUE 3.0
November 1998
PIN 1A INDEX MARK
ON TOP SURFACE
A
B
C
D
E
F
G
H
J
K
L
11 10 9 8 7 6 5 4 3 2 1
AC84
FEATURES
s 16-bit, 32 instruction 20MHz ALU
s 16-bit, 20MHz Logical, Arithmetic or Barrel Shifter
s Independent ALU and Shifter Operation
s 4 x 16-bit On Chip Scratchpad Registers
s Multiprecision Operation; e.g. 200ns 64-bit
Accumulate
s Three Port Structure with Three Internal Feedback
Paths Eliminates I/O Bottlenecks
s Block Floating Point Support
s 300mW Maximum Power Dissipation
s 84-pin Pin Grid Array or 84 Contact LCC Packages
or 100 pin Ceramic Quad Flat Pack
APPLICATIONS
s Digital Signal Processing
s Array Processing
s Graphics
s Database Addressing
s High Speed Arithmetic Processors
ASSOCIATED PRODUCTS
PDSP16112 Complex Multiplier
PDSP16116 16 x 16 Complex Multiplier
PDSP16318 Complex Accumulator
PDSP16330 Pythagoras Processor
GC100
Fig.1 Pin connections - bottom view
ORDERING INFORMATION
PDSP1601 MC GGCR 10MHz MIL883 Screened -
QFP package
PDSP1601A BO AC
20MHz Industrial - PGA
package
N.B Further details of the Military grade part are
available in a separate datasheet (DS3763)
1






PDSP1601A Datasheet, Funktion
PDSP1601/PDSP1601A
Divide by Two
The Barrel Shifter
The ALU has four (A2SGN, A2RAL, A2RAR, A2RSX)
instructions used for right shifting (dividing by two) extended
precision words. These words, (up to 64 bits) may be stored
in the two on-chip register files. When the least significant 16
bit word is shifted, the vacant MSB must be filled with the LSB
from the next most significant 16 bit byte. This is achieved via
the A2RAL, A2RAR or A2RSX instructions which indicate the
source of the new MSB (see ALU INSTRUCTION SET).
When the most significant 16 bit byte is right shifted, the
MSB must be filled with a duplicate of the original MSB so as
to maintain the correct sign (Sign Extension). This operation
is achieved via the A2SGN instruction (see Table 1).
Constants
The ALU has four instructions (OPONE, OPBYT, OPNIB,
OPALT) that force a constant value onto the ALU output.
These values are primarily intended to be used as masks, or
the seeds for mask generation, for example, the OPONE
instruction will set a single bit in the least significant position.
This bit may be rotated any where in the 16 bit field by the
Barrel Shifter, allowing the AND function of the ALU to perform
bit-pick operations on input data.
CLR
The ALU instruction CLRXX is used as a Master Reset for
the entire device. This instruction has the effect of:
The Barrel Shifter supports 16 instructions as detailed in
Table 2. The input to the Barrel Shifter is selected by the S
MUX. Data will fall through from the selected register, through
the S MUX and the Barrel Shifter to the shifter output register
file in 50ns for the PDSP1601A (100ns for the PDSP1601).
The Barrel Shifter instructions are latched, such that the
instructions will not start executing until the rising edge of CLK
latches the instruction into the device.
The Barrel Shifter is capable of Logical Arithmetic or Barrel
Shifts in either direction.
A. Logical shifts discard bits that exit the 16 bit field and fill
spaces with zeros.
B. Arithmetic shifts discard bits that exit the 16 bit field and
fill spaces with duplicates of the original MSB.
C. Barrel Shifts rotate the 16 bit fields such that bits tha exit
the 16 bit field to the left or right reappear in the vacant
spaces on the right or left.
The amount of shift applied is encoded onto the 4 bit Barrel
Shifter input as illustrated in Table 3. The type of shift and the
amount are determined by the shift control block. The shift
control block (see Fig.3) accepts and decodes the four bit ISO-
3 instruction. The shift control block contains a priority
encoder and two user programmable 4 bit registers R1 and
R2.
There are four possible sources of shift value that can be
passed onto the Barrel Shifter, there are:
1. Clearing ALU and Barrel Shifter register files to zero.
2. Clearing A and B port input registers to zero.
3. Clearing the R1 and R2 shift control registers to zero.
4. Clearing the internally registered CO bit to zero.
5. Programming the BFP flag to detect overflow conditions.
Inst IS3-IS0 Mnemonic
1. The Priority Encoder
2. The SV input
3. The R1 register
4. The R2 register
Operation
I/O
0 0000 LSRSV Logical Shift Right by SV
1 0001 LSLSV Logical Shift Left by SV
2 0010 BSRSV Barrel Shift Right by SV
3 0011 BSLSV Barrel Shift Left by SV
4 0100 LSRR1 Logical Shift Right by R1
5 0101 LSLR1 Logical Shift Left by R1
6 0110 LSRR2 Logical Shift Right by R2
7 0111 LSLR2 Logical Shift Left by R2
8 1000 LR1SV Load Register 1 From SV
9 1001 LR2SV Load Register 2 From SV
A 1010 ASRSV Arithmetic Shift Right by SV
B 1011 ASRR1 Arithmetic Shift Right by R1
C 1100 ASRR2 Arithmetic Shift Right by R2
D 1101 NRMXX Normalise Output PE
E 1110 NRMR1 Normalise Output PE, Load R1
F 1111 NRMR2 Normalise Output PE, Load R2
I
I
I
I
X
X
X
X
I
I
I
X
X
O
O
O
KEY
SV
R1
R2
PE
I
O
X
6
Table 2 Barrel shifter instructions
= Shift Value
= Register 1
= Register 2
= Priority Encoder Output
=> SV Port operates as an Input
=> SV Port operates as an Output
=> SV Port in a High Impedance State
MNEMONICS
LSXYY Logical Shift, X = Direction YY = Source of Shift Value
BSXYY Barrel Shift, X = Direction YY = Source of Shift Value
ASXYY Arithmetic Shift, X = Direction YY = Source of Shift Value
LXXYY Load
XX = Target YY = Source
NRMYY Normalise by PE, Output PE value on SV Port, Load YY Reg

6 Page









PDSP1601A pdf, datenblatt
PDSP1601/PDSP1601A
Mnemonic
LR1SV
LR2SV
ASRSV
ASRR1
ASRR2
NRMXX
NRMR1
NRMR2
Op Code
<8>
<9>
<A>
<B>
<C>
<D>
<E>
<F>
Function
On the rising edge of CLK at the end of the cycle in which this instruction is executing, the
R1 register will be loaded with the data present on the SV port. The input to the Barrel
Shifter will be passed onto the output unshifted.
On the rising edge of CLK at the end of the cycle in which this instruction is executing, the
R2 register will be loaded with the data present on the SV port. The input to the Barrel
Shifter will be passed onto the output unshifted.
The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by
the magnitude of the four bit number present in the SV register. The LSBs are discarded,
and the vacant MSBs are filled with duplicates of the original MSB. (Sign Extension).
The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by
the magnitude of the four bit number resident within the R1 register. The LSBs are
discarded, and the vacant MSBs are filled with duplicates of the original MSB.
(Sign Extension).
The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by
the magnitude of the four bit number resident within the R2 register. The LSBs are
discarded, and the vacant MSBs are filled with duplicates of the original MSB.
(Sign Extension).
The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the
magnitude of the four bit number output from the Priority Encoder. This value is also output
on the SV
The effect
poof rtth(isproopveidraetdioSnVisOtEo
is low).
left shift
the
input
by
the
necessary
amount
(max 15 places) to result in the MSB and the next most significant bit being different. This
has the effect of eliminating unnecessary Sign Bits, and hence Normalising the input data.
The MSBs shifted out to the left are discarded, and the vacant LSBs on the right are filled
with zeros.
The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the
magnitude of the four bit number output from the Priority Encoder. This value is also loaded
into the
is low).
R1
register
at
the
end
of
the
cycle,
and
is
output
on
the
SV
port
(provided
SVOE
The effect of this operation is to left shift the input by the necessary amount
(max 15 places) to result in the MSB and the next most significant bit being different. This
has the effect of eliminating unnecessary Sign Bits, and hence Normalising the input data.
The MSBs shifted out to the left are discarded, and the vacant LSBs on the right are filled
with zeros.
The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the
magnitude of the four bit number output from the Priority Encoder. This value is also loaded
into the
is low).
R2
register
at
the
end
of
the
cycle,
and
is
output
on
the
SV
port
(provided
SVOE
The effect of this operation is to left shift the input by the necessary amount
(max 15 places) to result in the MSB and the next most significant bit being different. This
has the effect of eliminating unnecessary Sign Bits, and hence Normalising the input data.
The MSBs shifted out to the left are discarded, and the vacant LSBs on the right are filled
with zeros.
12

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