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ADC12DS095 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC12DS095
Beschreibung (ADC12DSxxx) A/D Converter
Hersteller National Semiconductor
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Gesamt 30 Seiten
ADC12DS095 Datasheet, Funktion
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ADVANCE INFORMATION
February 2007
ADC12DS065/ADC12DS080/ADC12DS095/ADC12DS105
Dual 12-Bit, 65/80/95/105 MSPS A/D Converter with Serial
LVDS outputs
General Description
NOTE: This is Advance Information for products current-
ly in development. ALL specifications are design targets
and are subject to change.
The ADC12DS065, ADC12DS080, ADC12DS095, and AD-
C12DS105 are high-performance CMOS analog-to-digital
converters capable of converting two analog input signals into
12-bit digital words at rates up to 65/80/95/105 Mega Samples
Per Second (MSPS) respectively. The digital outputs are se-
rialized and provided on differential LVDS signal pairs. These
converters use a differential, pipelined architecture with digital
error correction and an on-chip sample-and-hold circuit to
minimize power consumption and the external component
count, while providing excellent dynamic performance. A
unique sample-and-hold stage yields a full-power bandwidth
of 1 GHz. The ADC12DS065/080/095/105 may be operated
from a single +3.3V power supply and consumes low power.
A power-down feature reduces the power consumption to
very low levels while still allowing fast wake-up time to full
operation. The differential inputs provide a 2V full scale dif-
ferential input swing. A stable 1.2V internal voltage reference
is provided, or the ADC12DS065/080/095/105 can be oper-
ated with an external 1.2V reference. Output data format
(offset binary versus 2's complement) and duty cycle stabi-
lizer are pin-selectable. The duty cycle stabilizer maintains
performance over a wide range of clock duty cycles.
The ADC12DS065/080/095/105 is available in a 60-lead LLP
package and operates over the industrial temperature range
of −40°C to +85°C.
Features
1 GHz Full Power Bandwidth
Internal sample-and-hold circuit and precision reference
Low power consumption
Clock Duty Cycle Stabilizer
Single +3.3V supply operation
Offset binary or 2's complement output data format
Serial LVDS Outputs
60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)
Key Specifications
For ADC12DS105
Resolution
Conversion Rate
SNR (fIN = 240 MHz)
SFDR (fIN = 240 MHz)
Full Power Bandwidth
Power Consumption
12 Bits
105 MSPS
67 dBFS (typ)
83 dBFS (typ)
1 GHz (typ)
1060 mW (typ)
Applications
High IF Sampling Receivers
Wireless Base Station Receivers
Test and Measurement Equipment
Communications Instrumentation
Portable Instrumentation
Connection Diagram
© 2007 National Semiconductor Corporation 202117
20211701
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ADC12DS095 Datasheet, Funktion
Pin No.
53
46
30
Symbol
SDO
ORA
ORB
24 DLL_Lock
ANALOG POWER
8, 16, 17, 58,
60
VA
1, 4, 12, 15,
Exposed Pad
DIGITAL POWER
AGND
26, 40, 49, 50
VDR
25, 39, 51
DRGND
Equivalent Circuit
Description
Serial Data-Out: Serial data are shifted out of the device on this pin
while SCSb signal is asserted. This output is in tri-state mode when
SCSb is deasserted.
Overrange. These CMOS outputs are asserted logic-high when
their respective channel’s data output is out-of-range in either high
or low direction.
DLL_Lock Output. When the internal DLL is locked to the input
CLK, this pin outputs a logic high. If the input CLK is changed
abruptly, the internal DLL may become unlocked and this pin will
output a logic low. Cycle Reset_DLL (pin 28) to re-lock the DLL to
the input CLK.
Positive analog supply pins. These pins should be connected to a
quiet source and be bypassed to AGND with 0.1 µF capacitors
located close to the power pins.
The ground return for the analog supply.
Positive driver supply pin for the output drivers. This pin should be
connected to a quiet voltage source and be bypassed to DRGND
with a 0.1 µF capacitor located close to the power pin.
The ground return for the digital output driver supply. This pins
should be connected to the system digital ground, but not be
connected in close proximity to the ADC's AGND pins.
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ADC12DS095 pdf, datenblatt
Symbol
Parameter
H3 Third Harmonic Distortion
SINAD Signal-to-Noise and Distortion Ratio
Conditions
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
Typical
(Note 10) Limits
−90
−88
−83
71.1
69.8
67.7
Units
(Limits)
(Note 2)
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
ADC12DS080 Logic and Power Supply Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V,
fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN TA TMAX. All other
limits apply for TA = 25°C (Notes 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10) Limits
Units
(Limits)
DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B,SCSb,SPI_EN,SCLK,SDI,TEST,WAM,DLC)
VIN(1)
Logical “1” Input Voltage
VD = 3.6V
VIN(0)
Logical “0” Input Voltage
VD = 3.0V
IIN(1)
Logical “1” Input Current
VIN = 3.3V
IIN(0)
Logical “0” Input Current
VIN = 0V
CIN Digital Input Capacitance
DIGITAL OUTPUT CHARACTERISTICS (ORA,ORB,SDO)
2.0 V (min)
0.8 V (max)
10 µA
−10 µA
5 pF
VOUT(1) Logical “1” Output Voltage
VOUT(0) Logical “0” Output Voltage
+ISC Output Short Circuit Source Current
−ISC Output Short Circuit Sink Current
COUT Digital Output Capacitance
POWER SUPPLY CHARACTERISTICS
IOUT = −0.5 mA , VDR = 1.8V
IOUT = 1.6 mA, VDR = 1.8V
VOUT = 0V
VOUT = VDR
1.2 V (min)
0.4 V (max)
−10 mA
10 mA
5 pF
IA Analog Supply Current
IDR Digital Output Supply Current
Power Consumption
Full Operation
Full Operation
200 mA (max)
56 mA
845 mW (max)
Power Down Power Consumption
30 mW
ADC12DS080 Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF = +1.2V,
fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal
amplitude. Boldface limits apply for TMIN TA TMAX. All other limits apply for TA = 25°C (Notes 8, 9)
Symb
Parameter
Conditions
Typical
(Note 10) Limits
Units
(Limits)
Maximum Clock Frequency
In Single-Lane Mode
In Dual-Lane Mode
65
80
MHz (max)
Minimum Clock Frequency
In Single-Lane Mode
In Dual-Lane Mode
25
52.5
MHz (min)
tCONV Conversion Latency
Single-Lane Mode
Dual-Lane, Offset Mode
Dual-Lane, Word Aligned Mode
7.5
8 Clock Cycles
9
tAD Aperture Delay
tAJ Aperture Jitter
0.6 ns
0.1 ps rms
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