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CDP1833C Schematic ( PDF Datasheet ) - Intersil

Teilenummer CDP1833C
Beschreibung CMOS 7-Bit Latch and Decoder Memory Interface
Hersteller Intersil
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Gesamt 6 Seiten
CDP1833C Datasheet, Funktion
March 1997
www.DataSheet4U.com
CDP1883,
CDP1883C
CMOS 7-Bit Latch
and Decoder Memory Interfaces
Features
• Performs Memory Address Latch and Decoder Func-
tions Multiplexed or Non-Multiplexed
• Interfaces Directly with the CDP1800-Series Micropro-
cessors
• Allows Decoding for Systems Up to 32K Bytes
Ordering Information
5V 10V
CDP1883CE CDP1883E
TEMP.
RANGE
-40oC to
+85oC
PKG.
PACKAGE NO.
PDIP
E20.3
Description
The CDP1883 is a CMOS 7-bit memory latch and decoder
circuit intended for use in CDP1800-series microprocessor
systems. It can serve as a direct interface between the multi-
plexed address bus of this system and up to four 8K x 8-bit
memories to implement a 32K-byte memory system. With
four 4K x 8-bit memories, a 16K-byte system can be
decoded.
The device is also compatible with non-multiplexed address
bus microprocessors. By connecting the clock input to VDD,
the latches are in the data-following mode and the decoded
outputs can be used in general-purpose memory-system
applications.
The CDP1833 is compatible with CDP1800-series micropro-
cessors operating at maximum clock frequency.
The CDP1883 and CDP1883C are functionally identical.
They differ in that the CDP1883 has a recommended operat-
ing voltage range of 4V to 10.5V and the C version has a
recommended operating voltage range of 4V to 6.5V.
The CDP1883 and CDP1883C are supplied in 20 lead dual-
in-line plastic packages (E Suffix).
Pinout
CDP1883, CDP1883C
(PDIP)
TOP VIEW
CLOCK 1
MA0 2
MA1 3
MA2 4
MA3 5
MA4 6
MA5 7
MA6 8
CE 9
VSS 10
20 VDD
19 A8
18 A9
17 A10
16 A11
15 A12
14 CS0
13 CS1
12 CS2
11 CS3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-129
File Number 1507.2






CDP1833C Datasheet, Funktion
WAIT
CLR
www.DataSheet4U.com
TPA
CDP1800
SERIES
CPU
MRD
MWR
CDP1883, CDP1883C
ADDRESS BUS
A0 - A7
TPA
CDP1837C
4K x 8
ROM
CEO
MRD
A0 - A6
CLK
CDP1883
LATCH/
DECODER
CS0
CE CS1
CS2
CS3
A8 - A12
A0 - A7
CDM6264
8K x 8
RAM
CE
OE
WE
DATA BUS
FIGURE 2. MINIMUM CDP1800-SYSTEM USING THE CDP1883 INTERFACE WITH AN 8K X 8-BIT MEMORY
WAIT
CLR
CDP1883
LATCH/
DECODER
CLK
CS3
CS2
CE CS1
CS0
MA0 - MA6
A8 - A12
ADDRESS BUS
TPA
CDP1800
SERIES
CPU
ADDRESS BUS
MRD
A8 - A12
CE
A0 - A7
CDM5364
8K x 8
ROM
A8 - A12
CE
A0 - A7
CDM5364
8K x 8
ROM
A8 - A12
CE
A0 - A7
CDM5364
8K x 8
ROM
DATA BUS
FIGURE 3. 32K-BYTE ROM SYSTEM USING THE CDP1883
4-134
A8 - A12
CE
A0 - A7
CDM5364
8K x 8
ROM

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