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DAC8560 Schematic ( PDF Datasheet ) - Burr-Brown

Teilenummer DAC8560
Beschreibung DIGITAL-TO-ANALOG CONVERTER
Hersteller Burr-Brown
Logo Burr-Brown Logo 




Gesamt 29 Seiten
DAC8560 Datasheet, Funktion
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BurrĆBrown Products
from Texas Instruments
DAC8560
DAC8560
16-Bit, Ultra-Low Glitch, Voltage Output
DIGITAL-TO-ANALOG CONVERTER
with 2.5V, 2ppm/°C Internal Reference
SLAS464 – DECEMBER 2006
FEATURES
Relative Accuracy: 4LSB
Glitch Energy: 0.15nV-s
MicroPower Operation: 510µA at 2.7V
Internal Reference:
2.5V Reference Voltage (enabled by default)
0.02% Initial Accuracy
2ppm/°C Temperature Drift (typ)
5ppm/°C Temperature Drift (max)
20mA Sink/Source Capability
Power-On Reset to Zero
Power Supply: +2.7V to +5.5V
16-Bit Monotonic Over Temperature Range
Settling Time: 10µs to ±0.003% FSR
Low-Power Serial Interface with
Schmitt-Triggered Inputs
On-Chip Output Buffer Amplifier with
Rail-to-Rail Operation
Power-Down Capability
Drop-In Compatible With DAC8531/01 and
DAC8550/51
Temperature Range: –40°C to +105°C
Available in a Tiny MSOP-8 Package
APPLICATIONS
Process Control
Data Acquisition Systems
Closed-Loop Servo-Control
PC Peripherals
Portable Instrumentation
DESCRIPTION
The DAC8560 is a low-power, voltage output, 16-bit
digital-to-analog converter (DAC). The DAC8560
includes a 2.5V, 2ppm/°C internal reference (enabled
by default), giving a full-scale output voltage range of
2.5V. The internal reference has an initial accuracy
of 0.02% and can source up to 20mA at the VREF pin.
The device is monotonic, provides very good
linearity, and minimizes undesired code-to-code
transient voltages (glitch). The DAC8560 uses a
versatile 3-wire serial interface that operates at clock
rates up to 30MHz. It is compatible with standard
SPI™, QSPI™, Microwire™, and digital signal
processor (DSP) interfaces.
The DAC8560 incorporates a power-on-reset circuit
that ensures the DAC output powers up at zero-scale
and remains there until a valid code is written to the
device. The DAC8560 contains a power-down
feature, accessed over the serial interface, that
reduces the current consumption of the device to
1.2µA at 5V.
The low-power consumption, internal reference, and
small footprint make this device ideal for portable,
battery-operated equipment. The power consumption
is 2.6mW at 5V, reducing to 6µW in power-down
mode.
The DAC8560 is available in an MSOP-8 package.
FUNCTIONAL BLOCK DIAGRAM
VDD
VREF
SYNC
SCLK
DIN
2.5V
Reference
Ref (+)
16-Bit DAC
16
DAC Register
16
Shift Register
PWD
Control
Resistor
Network
GND
VFB
VOUT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated






DAC8560 Datasheet, Funktion
DAC8560
SLAS464 – DECEMBER 2006
SERIAL WRITE OPERATION
SCLK
SYNC
DIN
1
t8
t4
DB23
t6
t5
t3
t1
24
t2
t7
t10
DB0
t9
www.ti.com
DB23
TIMING REQUIREMENTS(1)(2)
VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t1(3) SCLK cycle time
t2 SCLK HIGH time
t3 SCLK LOW time
t4 SYNC to SCLK rising edge setup time
t5 Data setup time
t6 Data hold time
t7 SCLK falling edge to SYNC rising edge
t8 Minimum SYNC HIGH time
t9 24th SCLK falling edge to SYNC falling edge
t10
SYNC rising edge to 24th SCLK falling edge
(for successful SYNC interrupt)
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
MIN TYP MAX UNIT
50
ns
33
13
ns
13
22.5
ns
13
0
ns
0
5
ns
5
4.5
ns
4.5
0
ns
0
50
ns
33
100
ns
100
15
ns
15
(1) All input signals are specified with tR = tF = 3ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 30MHz at VDD = 3.6V to 5.5V and 20MHz at VDD = 2.7V to 3.6V.
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DAC8560 pdf, datenblatt
DAC8560
SLAS464 – DECEMBER 2006
TYPICAL CHARACTERISTICS: DAC at VDD = 5V (continued)
At TA = +25°C, external reference used, and DAC output not loaded, unless otherwise noted.
www.ti.com
GLITCH ENERGY:
5V, 1LSB STEP, RISING EDGE
GLITCH ENERGY:
5V, 1LSB STEP, FALLING EDGE
VDD = 5V
Ext VREF = 4.096V
From Code: 7FFFh
To Code: 8000h
Glitch: 0.08nV-s
Time (400ns/div)
Figure 31.
GLITCH ENERGY:
5V, 16LSB STEP, RISING EDGE
VDD = 5V
Ext VREF = 4.096V
From Code: 8000h
To Code: 8010h
Glitch: 0.04nV-s
Time (400ns/div)
Figure 33.
GLITCH ENERGY:
5V, 256LSB STEP, RISING EDGE
VDD = 5V
Ext VREF = 4.096V
From Code: 8000h
To Code: 80FFh
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Figure 35.
VDD = 5V
Ext VREF = 4.096V
From Code: 8000h
To Code: 7FFFh
Glitch: 0.16nV-s
Measured Worst Case
Time (400ns/div)
Figure 32.
GLITCH ENERGY:
5V, 16LSB STEP, FALLING EDGE
VDD = 5V
Ext VREF = 4.096V
From Code: 8010h
To Code: 8000h
Glitch: 0.08nV-s
Time (400ns/div)
Figure 34.
GLITCH ENERGY:
5V, 256LSB STEP, FALLING EDGE
VDD = 5V
Ext VREF = 4.096V
From Code: 80FFh
To Code: 8000h
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Figure 36.
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