PDF RMPA0966 Data sheet ( Hoja de datos )

Número de pieza	RMPA0966
Descripción	Power Amplifier Module
Fabricantes	Fairchild Semiconductor
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No Preview Available ! PRELIMINARY November 2005 RMPA0966 i-Lo™ Cellular CDMA, CDMA2000-1X and WCDMA Power Ampliﬁer Module Features ■ 42% CDMA/WCDMA efﬁciency at +28 dBm Pout ■ 21% CDMA/WCDMA efﬁciency (56 mA total current) at +16 dBm Pout ■ Meets HSDPA performance requirements ■ 50% AMPS mode efﬁciency at +31 dBm Pout ■ Low quiescent current (Iccq): 15 mA in low-power mode ■ Single positive-supply operation with low power and shutdown modes • 3.4V typical Vcc operation • Low Vref (2.85V) compatible with advanced handset chipsets ■ Compact Lead-free compliant LCC package – (4.0 X 4.0 x 1.0 mm nominal) ■ Industry standard pinout ■ Internally matched to 50 Ohms and DC blocked RF input/output ■ Meets IS-95/CDMA2000-1XRTT/WCDMA performance requirements Device General Description The RMPA0966 Power Ampliﬁer Module (PAM) is Fairchild’s lat- est innovation in 50 Ohm matched, surface mount modules tar- geting Cellular CDMA/WCDMA/HSDPA, AMPS and Wireless Local Loop (WLL) applications. Answering the call for ultra-low DC power consumption and extended battery life in portable electronics, the RMPA0966 uses novel proprietary circuitry to dramatically reduce ampliﬁer current at low to medium RF out- put power levels (<+16 dBm), where the handset most often operates. A simple two-state Vmode control is all that is needed to reduce operating current by more than 60% at 16 dBm output power, and quiescent current (Iccq) by as much as 70% com- pared to traditional power-saving methods. No additional cir- cuitry, such as DC-to-DC converters, are required to achieve this remarkable improvement in ampliﬁer efﬁciency. Further, the 4x4x1.0 mm LCC package is pin-compatible and a drop-in replacement for last generation 4x4 mm PAMs widely used today, minimizing the design time to apply this performance- enhancing technology. The multi-stage GaAs Microwave Mono- lithic Integrated Circuit (MMIC) is manufactured using Fairchild RF’s InGaP Heterojunction Bipolar Transistor (HBT) process. Functional Block Diagram Vref 1 Vmode 2 GND 3 RF IN 4 Vcc1 5 MMIC (Top View) BIAS/MODE SWITCH INPUT MATCH 10 GND 9 GND OUTPUT MATCH 8 RF OUT 7 GND 6 Vcc2 11 (paddle ground on package bottom) ©2005 Fairchild Semiconductor Corporation RMPA0966 i-Lo™ Rev. A 1 www.fairchildsemi.com 1 page Package Outline I/O 1 INDICATOR 1 (4.00mm +.100 –.050 ) SQUARE 2 3 4 5 TOP VIEW 10 9 8 7 6 1.1mm MAX. .25mm TYP. FRONT VIEW 3.50mm TYP. See Detail A .30mm TYP. .85mm TYP. 2 11 1 1.08mm 1.84mm BOTTOM VIEW 3.65mm .18mm Signal Descriptions Pin # 1 2 3 4 5 6 7 8 9 10 11 Signal Name Vref Vmode GND RF In Vcc1 Vcc2 GND RF Out GND GND GND Description Reference Voltage High Power/Low Power Mode Control Ground RF Input Signal Supply Voltage to Input Stage Supply Voltage to Output Stage Ground RF Output Signal Ground Ground Paddle Ground .40mm .10mm .10mm .40mm .45mm DETAIL A. TYP. RMPA0966 i-Lo™ Rev. A 5 www.fairchildsemi.com 5 Page

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