Datenblatt-pdf.com


A3985 Schematic ( PDF Datasheet ) - Allegro MicroSystems

Teilenummer A3985
Beschreibung Digitally Programmable Dual Full-Bridge MOSFET Driver
Hersteller Allegro MicroSystems
Logo Allegro MicroSystems Logo 




Gesamt 15 Seiten
A3985 Datasheet, Funktion
www.DataSheet4U.com
A3985
Digitally Programmable
Dual Full-Bridge MOSFET Driver
Features and Benefits
Serial interface for full digital control
Dual full-bridge gate drive for N-channel MOSFETs
Dual 6-bit DAC current reference
Operation over 12 to 50 V supply voltage range
Synchronous rectification
Cross-conduction protection
Adjustable mixed decay
Fixed off-time PWM current control
Low-current idle mode
Package: 38 pin TSSOP (suffix LD)
Description
The A3985 is a flexible dual full-bridge gate driver suitable
for driving a wide range of higher power industrial bipolar 2-
phase stepper motors or 2-phase brushless dc motors. It can
also be used to drive two individual torque motors or solenoid
actuators. Motor power is provided by external N-channel power
MOSFETs at supply voltages from 12 to 50 V.
Full digital control is provided by two serially-accessible
registers that allow programming of off-time, blank-time,
dead-time, mixed decay ratios, synchronous rectification,
master clock source selection, and division ratio and idle
mode. All internal timings are derived from a master clock
that can be generated on-chip or provided by an external
clock such as the system clock of the master controller. A
programmable divider allows for a wide range of external
system clock frequencies.
The internal fixed off-time PWM current-control timing is
programmed via the serial interface to operate in slow, fast,
and mixed current-decay modes. The desired load-current level
and direction is set via the serial port with a direction bit and
two 6-bit linear DACs in conjunction with a reference voltage.
The seven bits of control allow maximum flexibility in torque
Approximate size
Continued on the next page…
Typical Application
3985-DS






A3985 Datasheet, Funktion
A3985
Digitally Programmable
Dual Full-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS, continued, at TA = 25°C, VDD = 5 V, VBB = 12 to 50 V, unless noted otherwise
Characteristics
Symbol
Test Conditions
Min. Typ. Max. Units
Serial Data Timing
Serial Clock High Time
tSCKH
50 – – ns
Serial Clock Low Time
tSCKL
50 – – ns
Strobe Lead Time
tSTLD
30 – – ns
Strobe Lag Time
tSTLG
30 – – ns
Strobe High Time
tSTRH
150
ns
Data Out Enable Time
tSDOE
– – 40 ns
Data Out Disable Time
tSDOD
– – 30 ns
Data Out Valid Time from SCK Falling
tSDOV
– – 40 ns
Data Out Hold Time from SCK Falling
tSDOH
5 – – ns
Data In Set-up Time to SCK Rising
tSDIS
15 – – ns
Data In Hold Time from SCK Rising
tSDIH
10 – – ns
WC Set-up Time to STR Rising
tSWCS
15 – – ns
WC Hold Time from STR Rising
tSWCH
50 – – ns
WC Hold Time from STR Falling
tSLWCH
30 – – ns
1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2Current Trip Point Error is the difference between actual current trip point and the target current trip point, referred to full
scale (100%) current: EITrip = 100 × (ITripActual – ITripTarget) / IFullScale %
Serial Data Timing Diagram
WC
STR
SCK
tSTLD
SDI
tSDOE
SDO
**
tSCKH
tSDIS
D18
tSDIH
tSDOV
tSDOH
D18*
tSLWCH
tSCKL
D17
D17*
Dx = Current data transfer block
Dx* = Previous data transfer block
** = Undefined, usually LSB from previous transfer
tSWCS
tSWCH
tSTLG
tSTRH
D0
tSDOD
D0*
Allegro MicroSystems, Inc.
6
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

6 Page









A3985 pdf, datenblatt
A3985
Digitally Programmable
Dual Full-Bridge MOSFET Driver
Note that, for tFD > tOFF , the device effectively operates in
full fast-decay mode.
D12 and D13 – Master Clock Control An internal
oscillator can be used for the timing functions, and if more
precise control is required, an external clock can be input to
the OSC terminal (for configuration information, refer to the
Functional Description section). To accommodate a wider
range of external system clocks, an internal divider is pro-
vided to generate the desired master clock frequency, fMCK ,
according to the following table:
D13 D12
00
Master Clock Source and fMCK
Internal oscillator*
01
External clock rate
10
External clock rate / 2
11
External clock rate / 4
*4 MHz typical, configurable with external resistor, ROSC.
D14 and D15 – Synchronous Rectification Two bits
are used to set the mode for sunchronous rectification. The
modes are described in the synchronous rectification section
of the Functional Description section.
D15 D14
00
01
10
11
Synchronous
Rectification Mode
Disabled
Disabled
Active
Passive
D16 and D17 – Reserved These bits are reserved for test-
ing and should be programmed to 0 during normal operation.
D18 – Idle Mode The device can be placed in a low power
mode by writing a 0 to D18. This disables the outputs and
the device draws a lower load supply current. The undervolt-
age monitor circuit remains active. When leaving idle mode,
D18 should be set to 1 for 1 ms before attempting to enable
any output driver.
Bit Assignments Table
Data Register
Word Bit
Function
D0 Register Select = 0
D1 Bridge 1, DAC bit 0 (LSB)
D2 Bridge 1, DAC bit 1
D3 Bridge 1, DAC bit 2
D4 Bridge 1, DAC bit 3
D5 Bridge 1, DAC bit 4
D6 Bridge 1, DAC bit 5 (MSB)
D7 Bridge 1, Phase
D8 Bridge 1, Mode
0 D9 Bridge 2, DAC bit 0 (LSB)
D10 Bridge 2, DAC bit 1
D11 Bridge 2, DAC bit 2
D12 Bridge 2, DAC bit 3
D13 Bridge 2, DAC bit 4
D14 Bridge 2, DAC bit 5 (MSB)
D15 Bridge 2, Phase
D16 Bridge 2, Mode
D17 Range Select bit 0
D18 Range Select bit 1
Control Register
Word Bit
Function
D0 Register Select = 1
D1 Blank-time bit 0 (LSB)
D2 Blank-time bit 1 (MSB)
D3 Off-time bit 0 (LSB)
D4 Off-time bit 1
D5 Off-time bit 2
D6 Off-time bit 3
D7 Off-time bit 4 (MSB)
D8 Fast-decay time bit 0 (LSB)
1 D9 Fast-decay time bit 1
D10 Fast-decay time bit 2
D11 Fast-decay time bit 3 (MSB)
D12 Master Clock Control bit 0 (LSB)
D13 Master Clock Control bit 1 (MSB)
D14 Synchronous Rectification Control bit 0 (LSB)
D15 Synchronous Rectification Control bit 1 (MSB)
D16 Reserved
D17 Reserved
D18 Idle Mode
Allegro MicroSystems, Inc.
12
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

12 Page





SeitenGesamt 15 Seiten
PDF Download[ A3985 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
A3980Automotive DMOS Microstepping Driver with TranslatorAllegro MicroSystems
Allegro MicroSystems
A3980KLPAutomotive DMOS Microstepping Driver with TranslatorAllegro MicroSystems
Allegro MicroSystems
A3982DMOS Stepper Motor DriverAllegro
Allegro
A3983DMOS Microstepping DriverAllegro MicroSystems
Allegro MicroSystems
A3984DMOS Microstepping DriverAllegro MicroSystems
Allegro MicroSystems

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche