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CAT93C46R Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT93C46R
Beschreibung 1-Kb Microwire Serial EEPROM
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 13 Seiten
CAT93C46R Datasheet, Funktion
www.DataSheet4U.com
CAT93C46R
1-Kb Microwire Serial EEPROM
FEATURES
I High speed operation: 4MHz @ 5V, 2MHz @ 1.8V
I 1.8V to 5.5V supply voltage range
I Selectable x8 or x16 memory organization
I Sequential read
I Software write protection
I Power-up inadvertent write protection
I Low power CMOS technology
I 1,000,000 program/erase cycles
I 100 year data retention
I Industrial temperature range
I RoHS-compliant 8-pin PDIP, SOIC, TSSOP and
8-pad TDFN packages
DESCRIPTION
The CAT93C46R is a 1-Kb CMOS Serial EEPROM
device which is organized as either 64 registers of
16 bits or 128 registers of 8 bits, as determined by the
state of the ORG pin. The CAT93C46R features
sequential read and self-timed internal write with auto-
clear. On-chip Power-On Reset circuitry protects the
internal logic against powering up in the wrong state.
In contrast to the CAT93C46, the CAT93C46R features
an internal instruction clock counter which provides
improved noise immunity for Write/Erase commands.
PIN CONFIGURATION
PDIP (L)
SOIC (V, X)
TSSOP (Y)
TDFN (VP2)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
SOIC (W)
NC 1
VCC
CS
SK
2
3
4
8 ORG
7 GND
6 DO
5 DI
PIN FUNCTIONS
Pin Name
CS
SK
Function
Chip Select
Clock Input
DI Serial Data Input
DO Serial Data Output
VCC
GND
Power Supply
Ground
ORG
NC
Memory Organization
No Connection
Note: When the ORG pin is connected to VCC, the x16 organization
is selected. When it is connected to ground, the x8 pin is selected.
If the ORG pin is left unconnected, then an internal pull-up device
will select the x16 organization.
FUNCTIONAL SYMBOL
VCC
ORG
CS
SK
DI
CAT93C46R
GND
DO
For Ordering Information details, see page 12.
* The Green & Gold seal identifies RoHS-compliant packaging, using NiPdAu
pre-plated lead frames.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1107, Rev. F






CAT93C46R Datasheet, Funktion
CAT93C46R
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN (see Design Note for details). The
falling edge of CS will start the self clocking clear and
data store cycle of the memory location specified in the
instruction. The clocking of the SK pin is not necessary
after the device has entered the self clocking mode.
The ready/busy status of the CAT93C46R can be
determined by selecting the device and polling the DO
pin. Since this device features Auto-Clear before write,
it is NOT necessary to erase a memory location before
it is written into.
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of tCSMIN after the proper number of clock pulses (see
Design Note). The falling edge of CS will start the self
clocking clear cycle of the selected memory location.
The clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The ready/
busy status of the CAT93C46R can be determined by
selecting the device and polling the DO pin. Once
cleared, the content of a cleared location returns to a
logical 1state.
Erase All
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of tCSMIN. The
falling edge of CS will start the self clocking clear cycle
of all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46R can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory bits return to a logical 1state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. (Note 1.) The ready/
busy status of the CAT93C46R can be determined by
selecting the device and polling the DO pin. It is not
necessary for all memory locations to be cleared before
the WRAL command is executed.
Design Note
With CAT93C46R, after the last data bit has been
sampled, Chip Select (CS) must be brought Low before
the next rising edge of the clock(SK) in order to start the
slef-timed high voltage cycle. This is important because
if the CS is brought low before or after this specific frame
window, the addressed location will not be programmed
or erased.
Figure 4. Write Instruction Timing
SK
CS
AN AN-1
DI 1 0 1
A0 DN
HIGH-Z
DO
tCS MIN
STATUS
VERIFY
D0
STANDBY
tSV BUSY
READY
tEW
tHZ
HIGH-Z
Doc. No. 1107, Rev. F
6
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

6 Page









CAT93C46R pdf, datenblatt
CAT93C46R
ORDERING INFORMATION
Prefix Device #
CAT 93C46R
Suffix
V
I
– G T3
Optional
Company ID
Product Number
93C46R
Temperature Range
I = Industrial (-40°C - 85°C)
Package
L = PDIP
V = SOIC, JEDEC
W = SOIC, JEDEC
X = SOIC, EIAJ(4)
Y = TSSOP
VP2 = TDFN (2X3mm)
Tape & Reel
T: Tape & Reel
2: 2000/Reel(4)
3: 3000/Reel
Lead Finish
G: NiPdAu
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT93C46RVI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel).
(4) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT93C46RXI-T2.
(5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
Doc. No. 1107, Rev. F
12
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

12 Page





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