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PDF A49FL004 Data sheet ( Hoja de datos )
| Número de pieza | A49FL004 | |
| Descripción | 4 Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory | |
| Fabricantes | AMIC Technology | |
| Logotipo |  |
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Preliminary
A49FL004
4 Mbit CMOS 3.3Volt-only Firmware Hub/LPC Flash Memory
Document Title
4 Mbit CMOS 3.3 Volt-only Firmware Hub/LPC Flash Memory
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
September 23, 2005
Remark
Preliminary
PRELIMINARY (September, 2005, Version 0.0)
AMIC Technology, Corp.
1 page  
Figure 3: BLOCK DIAGRAM
TBL
WP
INIT
FWH[3:0] or
LAD[3:0]
FWH4 or LFRAME
CLK
GPI[4:0]
A[10:0]
I/O[7:0]
WE
OE
R/C
IC
RST
FWH/LPC
Mode
Interface
A/A Mode
Interface
Erase/Program Voltage
Generator
High Voltage Switch
A49FL004
I/O Buffers
Control Logic
Data
Latch
Sense
Amp
Y-Decoder
X-decoder
Y - Gating
Memory Array
PRELIMINARY (September, 2005, Version 0.0)
4
AMIC Technology, Corp.
5 Page 
A49FL004
Table 4: LPC Memory Read Cycle Definition
Clock
Cycle
1
2
3-10
11
12
13
14-15
16
17
Field
START
CYCTYPE
+ DIR
ADDR
TAR0
TAR1
SYNC
DATA
TAR0
TAR1
LAD[3:0]
0000
010x
YYYY
1111
1111
(Float)
0000
1111
1111
1111
(Float)
Direction
Descriptions
Start of Cycle: “0000b” indicates the start of a LPC memory
IN
cycle. LFRAME must be active low (low) for the part to respond.
Only the last field latched before LFRAME transitions high will be
recognized.
Cycle Type: Indicates the type of a LPC memory read cycle.
IN
CYCTYPE: Bits 3-2 must be “01b” for memory cycle.
DIR: Bit 1 = “0b” indicates the type of cycle for Read. Bit 0 is
reserved.
Address Cycles: This is the 32-bit memory address. The
IN
addressed transfer most-significant nibble first and least-significant
nibble last. (i.e., a31-28 on LAD[3:0] first, and A3-A0 on LAD[3:0]
last).
IN Turn-Around cycle 0: The host has driven the bus to all”1”s and
Then Float then float the bus.
Float Turn-Around cycle 1: The A49FL004 takes control of the bus
then OUT during this cycle.
OUT
Sync: The device indicates the least-significant nibble of data byte
will be ready in next clock cycle.
OUT
Data Cycles: The 8-bits data transferred with least-significant
nibble first and most-significant nibble last. (i.e., I/O3 – I/O0 on
LAD[3:0] first, then I/O7 – I/O4 on LAD[3:0] last).
IN Turn-Around cycle 0: The host has driven the bus to all “1”s and
then Float then float the bus.
Float Turn-Around cycle 1: The A49FL004 resumes control of the bus
then OUT during this cycle.
Figure 6: LPC Single-Byte Read Waveforms
LCLK
LFRAME
LAD[3:0]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
START
CYCTYPE +
DIR
ADDRESS
TAR0 TAR1 SYNC
DATA
TAR0 TAR1
PRELIMINARY (September, 2005, Version 0.0)
10
AMIC Technology, Corp.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet A49FL004.PDF ] | |
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