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PDF ADS5231 Data sheet ( Hoja de datos )
| Número de pieza | ADS5231 | |
| Descripción | Analog-to-Digital Converter | |
| Fabricantes | Burr-Brown | |
| Logotipo |  |
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BurrĆBrown Products
from Texas Instruments
ADS5231
SBAS295A – JULY 2004 – REVISED JANUARY 2007
Dual, 12-Bit, 40MSPS, +3.3V
Analog-to-Digital Converter
FEATURES
• Single +3.3V Supply
• High SNR: 70.7dBFS at fIN = 5MHz
• Total Power Dissipation:
Internal Reference: 321mW
External Reference: 285mW
• Internal or External Reference
• Low DNL: ±0.3LSB
• Flexible Input Range: 1.5VPP to 2VPP
• TQFP-64 Package
APPLICATIONS
• Communications IF Processing
• Communications Base Stations
• Test Equipment
• Medical Imaging
• Video Digitizing
• CCD Digitizing
DESCRIPTION
The ADS5231 is a dual, high-speed, high dynamic
range, 12-bit pipelined analog-to-digital converter
(ADC). This converter includes a high-bandwidth
sample-and-hold amplifier that gives excellent
spurious performance up to and beyond the Nyquist
rate. The differential nature of the sample-and-hold
amplifier and ADC circuitry minimizes even-order
harmonics and gives excellent common-mode noise
immunity.
The ADS5231 provides for setting the full-scale
range of the converter without any external reference
circuitry. The internal reference can be disabled,
allowing low-drive, external references to be used for
improved tracking in multichannel systems.
The ADS5231 provides an over-range indicator flag
to indicate an input signal that exceeds the full-scale
input range of the converter. This flag can be used to
reduce the gain of front-end gain control circuitry.
There is also an output enable pin to allow for
multiplexing and testing on a printed circuit board
(PCB).
The ADS5231 employs digital error correction
techniques to provide excellent differential linearity
for demanding imaging applications. The ADS5231 is
available in a TQFP-64 package.
AVDD SDATA SEN SCLK SEL VDRV OEA
ADS5231
Serial
Interface
DISABLE_PLL
INA
VIN
INA
INT/EXT
CM
REFT
REFB
12-Bit
S/H Pipelined
ADC
Internal
Reference
Error
Correction
Logic
3-State
Output
Timing/Duty Cycle
Adjust (PLL)
D11A
·
·
·
D0A
OVRA
DVA
CLK
DVB
INB
VIN
S/H
INB
12-Bit
Pipelined
ADC
Error
Correction
Logic
3-State
Output
D11B
·
·
·
D0B
OVRB
STPD
OEB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
1 page  
ADS5231
www.ti.com
SBAS295A – JULY 2004 – REVISED JANUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
PARAMETER
ANALOG INPUT
Differential Input Capacitance
Analog Input Common-Mode Range
Differential Input Voltage Range
Voltage Overload Recovery Time(8)
Input Bandwidth
DIGITAL DATA INPUTS
Logic Family
VIH High-Level Input Voltage
VIL Low-Level Input Voltage
CIN Input Capacitance
DIGITAL OUTPUTS
Data Format
Logic Family
Logic Coding
Low Output Voltage (IOL = 50µA)
High Output Voltage (IOH = 50µA)
3-State Enable Time
3-State Disable Time
Output Capacitance
SERIAL INTERFACE
SCLK Serial Clock Input Frequency
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
TEST CONDITIONS
ADS5231
MIN TYP MAX
UNITS
Internal Reference
External Reference
–3dBFS Input, 25Ω Series
Resistance
3
VCM ± 0.05
2.02
2.02 × (VREFT – VREFB)
3
300
pF
V
VPP
VPP
CLK Cycles
MHz
VIN = 3.3V
VIN = 3.3V
+3V CMOS Compatible
2.2
0.6
3
V
V
pF
Straight Offset Binary(9)
CMOS
Straight Offset Binary or BTC
+0.4
+2.4
2
2
3
V
V
Clocks
Clocks
pF
20 MHz
20 40 MSPS
6 CLK Cycles
(8) A differential ON/OFF pulse is applied to the ADC input. The differential amplitude of the pulse in its ON (high) state is twice the
full-scale range of the ADC, while the differential amplitude of the pulse in its OFF (low) state is zero. The overload recovery time of the
ADC is measured as the time required by the ADC output code to settle within 1% of full-scale, as measured from its mid-code value
when the pulse is switched from ON (high) to OFF (low).
(9) Option for Binary Two’s Complement Output.
Submit Documentation Feedback
5
5 Page 
www.ti.com
PIN CONFIGURATION
Top View
ADS5231
SBAS295A – JULY 2004 – REVISED JANUARY 2007
TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
SEL 1
AGND 2
AVDD 3
GND 4
VDRV 5
OEB
GND
6
7
VDRV 8
OVRB 9
D0_B (LSB) 10
D1_B 11
D2_B 12
D3_B 13
D4_B 14
D5_B 15
D6_B 16
ADS5231
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 AGND
47 AGND
46 AVDD
45 STPD/SDATA
44 GND
43 VDRV
42 OEA/SCLK
41 MSBI/SEN
40 VDRV
39 OVRA
38 D11_A (MSB)
37 D10_A
36 D9_A
35 D8_A
34 D7_A
33 D6_A
NAME
AGND
AVDD
CLK
CM
D0_A (LSB)
D1_A
D2_A
D3_A
D4_A
D5_A
D6_A
D7_A
D8_A
D9_A
D10_A
D11_A (MSB)
D0_B (LSB)
PIN #
2, 47–49, 55, 58, 59, 61, 64
3, 46, 57
24
52
27
28
29
30
31
32
33
34
35
36
37
38
10
PIN DESCRIPTIONS
I/O DESCRIPTION
Analog Ground
Analog Supply
I Clock Input
Common-Mode Voltage Output
O Data Bit 12 (D0), Channel A
O Data Bit 11 (D1), Channel A
O Data Bit 10 (D2), Channel A
O Data Bit 9 (D3), Channel A
O Data Bit 8 (D4), Channel A
O Data Bit 7 (D5), Channel A
O Data Bit 6 (D6), Channel A
O Data Bit 5 (D7), Channel A
O Data Bit 4 (D8), Channel A
O Data Bit 3 (D9), Channel A
O Data Bit 2 (D10), Channel A
O Data Bit 1 (D11), Channel A
O Data Bit 12 (D0), Channel B
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11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet ADS5231.PDF ] | |
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