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A8436 Schematic ( PDF Datasheet ) - Allegro MicroSystems

Teilenummer A8436
Beschreibung Photoflash Capacitor Charger
Hersteller Allegro MicroSystems
Logo Allegro MicroSystems Logo 




Gesamt 14 Seiten
A8436 Datasheet, Funktion
www.DataSheet4U.com
A8436
Photoflash Capacitor Charger with IGBT Driver
Features and Benefits
Power with 1 Li+ or 2 Alkaline/NiMH/NiCAD batteries
Adjustable output voltage
>75% efficiency
Three levels of switch current limit: 1.0, 1.2, 1.4 A
Fast charge time
Charge complete indication
Integrated IGBT driver with trigger
No primary-side Schottky diode needed
Low-profile package (0.75 mm nominal height)
Package: 10 pin TDFN/MLP (suffix EJ)
Approximate Scale 1:1
Description
The A8436 is a highly integrated IC that charges photoflash
capacitors for digital and film cameras. It also features an
integrated IGBT driver that facilitates the flash discharge
function and saves board space.
To charge the photoflash capacitor, the A8436 integrates a
40 V, DMOS switch that drives the transformer in a flyback
topology, allowing optimized design with tight coupling and
high efficiency. A proprietary control scheme optimizes the
capacitor charging time. Low quiescent current and low
shutdown current further improve system efficiency and
extend battery life.
Three levels of switch current limit are provided: 1.0, 1.2,
and 1.4 A. The level is determined by configuring the ILIM
pin as grounded, floating, or pulled up to IC supply voltage,
respectively.
The CHARGE pin enables the A8436 and starts the charging
of the output capacitor. When the designated output voltage
is reached, the A8436 stops the charging until the CHARGE
pin is toggled again. Pulling the CHARGE pin low stops
charging. The D¯¯O¯¯N¯¯E¯¯ pin is an open-drain indicator of when
the designated output voltage is reached.
TheA8436 can be used with twoAlkaline/NiMH/NiCAD or one
single-cell Li+ battery connected to the transformer primary.
Connect the VIN pin to a 3.0 to 5.5 V supply, which can be
either the system rail or the Li+ battery, if used.
The A8436 is available in a very low profile (0.75 mm) 10-
terminal 3×3 mm MLP/TDFN package, making it ideal for
space-constrained applications. It is lead (Pb) free, with 100%
matte-tin leadframe plating.
Typical Applications
VBIAS 3.0 to 5.5 V
Two Alkaline/NiMH/NiCAD or one Li+ battery
or 1.5 to 5.5 V
VBATT
T1
D1 VOUT
One Li+ battery
VBATT or 3.0 to 5.5 V
T1 D1 VOUT
R5
100 k7
R4
10 k7
C1
0.1 μF
C2
4.7 μF
1.4 A
1.2 A (N.C.)
1.0 A
VIN
ILIM
SW
FB
R6
10 k7
DONE
A8436
CHARGE
TRIGGER
IGBTDRV
R7
10 k7
GND
To IGBT Gate
R1
R2
R3
COUT
Figure 1. Typical circuit with separate power supply to transformer
R5
100 k7
R4
10 k7
C1
0.1 μF
C2
4.7 μF
1.4 A
1.2 A (N.C.)
1.0 A
VIN
ILIM
SW
FB
R6
10 k7
DONE
A8436
CHARGE
TRIGGER
IGBTDRV
R7
10 k7
GND
To IGBT Gate
Figure 2. Typical circuit with single power supply
R1
R2
R3
COUT
A8436-DS, Rev. 3






A8436 Datasheet, Funktion
A8436
Photoflash Capacitor Charger with IGBT Driver
Performance Characteristics
Tests performed using application circuit shown in figure 6 (unless otherwise noted)
Charging Waveforms
VOUT
Symbol
C1
C4
t
Conditions
Parameter
VOUT
IBATT(Avg)
time
Parameter
VBATT
VBIAS
COUT
Units/Division
50 V
200 mA
1s
Value
2.5 V
3.3 V
100 μF
C4
C1
t
IBATT
Symbol
C1
C4
t
Conditions
Parameter
VOUT
IBATT(Avg)
time
Parameter
VBATT
VBIAS
COUT
Units/Division
50 V
200 mA
1s
Value
3.6 V
3.3 V
100 μF
C4
C1
t
VOUT
IBATT
Symbol
C1
C4
t
Conditions
Parameter
VOUT
IBATT(Avg)
time
Parameter
VBATT
VBIAS
COUT
Units/Division
50 V
200 mA
1s
Value
4.2 V
3.3 V
100 μF
C4
C1
VOUT
IBATT
t
Allegro MicroSystems, Inc.
6
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

6 Page









A8436 pdf, datenblatt
A8436
Photoflash Capacitor Charger with IGBT Driver
Applications Information
Transformer Design
Turns Ratio. The minimum transformer turns ratio, N,
(Secondary:Primary) should be chosen based on the following
formula:
N VOUT + VD_Drop
40 VBATT
(2)
where:
VOUT (V) is the required output voltage level,
VD_Drop (V) is the forward voltage drop of the output diode(s),
VBATT (V) is the transformer battery supply, and
40 (V) is the rated voltage for the internal MOSFET switch,
representing the maximum allowable reflected voltage from the
output to the SW pin.
For example, if VBATT is 3.5 V and VD_Drop is 1.7 V (which could
be the case when two high voltage diodes were in series), and the
desired VOUT is 320 V, then the turns ratio should be at least 8.9.
In a worst case, when VBATT is highest and VD_Drop and VOUT are
at their maximum tolerance limit, N will be higher. Taking VBATT
= 5.5 V, VD_Drop = 2 V, and VOUT = 320 V × 102 % = 326.4 V as
the worst case condition, N can be determined to be 9.5.
In practice, always choose a turns ratio that is higher than the
calculated value to give some safety margin. In the worst case
example, a minimum turns ratio of N = 10 is recommended.
Primary Inductance. The A8436 has a minimum switch off-time,
tOFF(min) , of 300 ns, to ensure correct SW node voltage sensing.
As a loose guideline when choosing the primary inductance,
LPrimary (μH), use the following formula:
LPrimary
300 ×109 ×VOUT
N × ISWLIM
.
(3)
Ideally, the charging time is not affected by transformer primary
inductance. In practice, however, it is recommended that a
primary inductance be chosen between 10 μH and 20 μH. When
LPrimary is much lower than 10 μH, the converter operates at
higher frequency, which increases switching loss proportionally.
This leads to lower efficiency and longer charging time. When
LPrimary is greater than 20 μH, the rating of the transformer must
be dramatically increased to handle the required power density,
and the series resistances are usually higher. A design that is
optimized to achieve a small footprint solution would have an
LPrimary of 12 to 14 μH, with minimized leakage inductance and
secondary capacitance, and minimized primary and secondary
series resistance. Please refer to the table Recommended
Components for more information.
Leakage Inductance and Secondary Capacitance. The trans-
former design should minimize the leakage inductance to ensure
the turn-off voltage spike at the SW node does not exceed the
40 V limit. An achievable minimum leakage inductance for this
application, however, is usually compromised by an increase in
parasitic capacitance. Furthermore, the transformer secondary
capacitance should be minimized. Any secondary capacitance is
multiplied by N2 when reflected to the primary, leading to high
initial current swings when the switch turns on, and to reduced
efficiency.
VBIAS 3.0 to 5.5 V
Two Alkaline/NiMH/NiCAD or one Li +
VBATT 1.5 to 5.5 V
T1
D1
VOUT
R5
100 k7
R6
10 k7
R4
10 k7
C1
0.1 μF
C2
4.7 μF
VIN
ILIM
SW
FB
DONE
A8436
CHARGE
TRIGGER
IGBTDRV
R7
10 k7
GND
To IGBT Gate
R1
150 k7
R2
150 k7
R3
1.2 k7
COUT
100 μF
330 V
Figure 6. Typical circuit for photoflash application. Configured for ISWLIM of 1.4 A.
Symbol
C1
C2
D1
T1
R1, R2
R3
R4, R5
R6, R7
Rating
0.1 μF, X5R or X7R, 10 V
4.7 μF, X5R or X7R, 10 V
Fairchild Semiconductor BAV23S
(dual diode connected in series)
Tokyo Coil Engineering T-16-024A,
LPrimary = 12 μH, N = 10.2
1206 resistors, 1 %
0603 resistor, 1 %
Pull-up resistors
Pull-down resistors
Allegro MicroSystems, Inc.
12
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

12 Page





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