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A3988 Schematic ( PDF Datasheet ) - Allegro MicroSystems

Teilenummer A3988
Beschreibung Quad DMOS Full Bridge PWM Motor Driver
Hersteller Allegro MicroSystems
Logo Allegro MicroSystems Logo 




Gesamt 13 Seiten
A3988 Datasheet, Funktion
www.DataSheet4U.com
A3988
Quad DMOS Full Bridge PWM Motor Driver
Features and Benefits
36 V output rating
4 full bridges
Dual stepper motor driver
High current outputs
3.3 and 5 V compatible logic supply
Synchronous rectification
Internal undervoltage lockout (UVLO)
Thermal shutdown circuitry
Crossover-current protection
Low profile QFN package
Packages
Package EV, 36 pin QFN
0.90 mm nominal height
with exposed thermal pad
Package JP, 48 pin LQFP
with exposed thermal pad
Approximate scale
Description
The A3988 is a quad DMOS full-bridge driver capable of
driving up to two stepper motors or four dc motors. Each
full-bridge output is rated up to 1.2 A and 36 V. The A3988
includes fixed off-time pulse width modulation (PWM) current
regulators, along with 2- bit nonlinear DACs (digital-to-analog
converters) that allow stepper motors to be controlled in full,
half, and quarter steps, and dc motors in forward, reverse, and
coast modes. The PWM current regulator uses the Allegro®
patented mixed decay mode for reduced audible motor noise,
increased step accuracy, and reduced power dissipation.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation.
Protection features include thermal shutdown with hysteresis,
undervoltage lockout (UVLO) and crossover current protection.
Special power up sequencing is not required.
The A3988 is supplied in two packages, EV and JP, with
exposed power tabs for enhanced thermal performance. The
EV is a 6 mm x 6 mm, 36 pin QFN package with a nominal
overall package height of 0.90 mm. The JP is a 7 mm × 7 mm
48 pin LQFP. Both packages are lead (Pb) free, with 100%
matte tin leadframe plating.
A3988DS, Rev.3
Microprocessor
VREF
VDD 3.3 V
0.1 μF
50 V
0.1 μF
50 V
100 μF
50 V
VMOTOR 32 V
0.22 μF
50 V
PHASE1
I01
I11
PHASE2
I02
I12
PHASE3
I03
I13
PHASE4
I04
I14
VREF1
VREF2
VREF3
VREF4
VDD
A3988
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B
SENSE2
SENSE1
SENSE3
SENSE4
Bipolar Stepper Motors
RS2
RS1
RS3
RS4
Figure 1. Typical application circuit






A3988 Datasheet, Funktion
A3988
Quad DMOS Full Bridge PWM Motor Driver
Synchronous Rectification When a PWM-off cycle is
triggered by an internal fixed off-time cycle, load current will
recirculate. The A3988 synchronous rectification feature will turn
on the appropriate MOSFETs during the current decay, and effec-
tively short out the body diodes with the low RDS(on) driver. This
significantly lowers power dissipation. When a zero current level
is detected, synchronous rectification is turned off to prevent
reversal of the load current.
Mixed Decay Operation The bridges operate in mixed
decay mode. Referring to figure 2, as the trip point is reached, the
device goes into fast decay mode for 30.1% of the fixed off-time
period. After this fast decay portion, tFD, the device switches
to slow decay mode for the remainder of the off-time. During
transitions from fast decay to slow decay, the drivers are forced
off for approximately 600 ns. This feature is added to prevent
shoot-through in the bridge. As shown in figure 2, during this
“dead time” portion, synchronous rectification is not active, and
the device operates in fast decay and slow decay only.
VPHASE
+
IOUT 0
See Enlargement A
Enlargement A
ITrip
Fixed Off-Time 30 μs
9 μs 21 μs
IOUT
FDDT
FDSR
SDDT
SDSR
SDDT
Figure 2. Mixed Decay Mode Operation
Allegro MicroSystems, Inc.
6
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

6 Page









A3988 pdf, datenblatt
A3988
Quad DMOS Full Bridge PWM Motor Driver
EV Package, 36 Pin QFN with Exposed Thermal Pad
Preliminary dimensions, for reference only
(reference JEDEC MO-220VJJD-1, except exposed thermal pad)
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P600X600X100-37V1M); adjust as necessary to
meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
36X
0.08 [.003] C
6.15 .242
5.85 .230
36
1
2A
36X
0.30
0.18
.012
.007
0.25 .010
NOM
1.15 .045
NOM
36
32X0.20 .008
MIN
0.50 .020
NOM
0.10 [.004] M C A B
0.05 [.002] M C
0.50 .020
0.75 .030
0.35 .014
4X0.20 .008
MIN
1
2
4X0.20 .008
MIN
C
4.15 .163
NOM
5.8 .228
NOM
5.8 .228
NOM
4.15 .163
NOM
R0.30 .012
REF
2
1
36
4.15 .163
NOM
A
B
6.15 .242
5.85 .230
SEATING C
PLANE
1.00 .039
0.80 .031
0.20 .008
REF
0.05 .002
0.00 .000
4.15 .163
NOM
Allegro MicroSystems, Inc.
12
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

12 Page





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