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PDF A6280 Data sheet ( Hoja de datos )
| Número de pieza | A6280 | |
| Descripción | 3-Channel Constant-Current LED Driver | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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A6280
3-Channel Constant-Current LED Driver
with Programmable PWM Control
Last Time Buy
This part is in production but has been determined to be
LAST TIME BUY. This classification indicates that the product is
obsolete and notice has been given. Sale of this device is currently
restricted to existing customer applications. The device should not be
purchased for new design applications because of obsolescence in the
near future. Samples are no longer available.
Date of status change:
A6280EA-T September 3, 2013
A6280EESTR-T June 3, 2013
Deadline for receipt of LAST TIME BUY orders: November 29, 2013
Recommended Substitutions:
For existing customer transition, and for new customers or new appli-
cations, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, LLC reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
1 page  
A6280
3-Channel Constant-Current LED Driver
with Programmable PWM Control
OPERATING CHARACTERISTICS, valid at TA = 25°C, VIN = 4.75 to 17.0 V, unless otherwise noted
Characteristic
Symbol
Test Conditions
Min. Typ.
ELECTRICAL CHARACTERISTICS
Quiescent Supply Current
Operating Supply Current
Load Supply Voltage
Undervoltage Lockout
VREG Voltage Range1
Output Current (any single output)
Output to Output Matching Error2
Output Voltage Range
Load Regulation (I%Diff / ∆VDS)
Output Leakage Current
Logic Input Voltage
Logic Input Voltage Hysteresis
IDD
IDD
VIN
VIN(UV)
VREG
IOUT
Err
VDS(min)
IDSX
VIH
VIL
fCLKIN = 0.0 Hz
fCLKIN = 5 Mhz
VIN rising
VIN falling
IO =15 mA, VIN = 17 V
REXT = 5 kΩ, scalar = 100%
REXT = 15 kΩ, scalar = 100%
Output to output variation—all outputs on, REXT = 5 kΩ
REXT = 5 kΩ, VDS = 1 to 3 V
VOH = 17 V
All digital inputs
–
–
4.75
3.5
3.0
4.6
135
45
–7
1.0
–
–
2.0
–
–
–
–
–
–
–
–
150.0
51
–
–
±1
–
–
–
150
Logic Output Voltage
Input Resistance
VOL VIN ≥ 5.0 V, IO = ±2 mA
VOH
RI
OEI pin, pull-up
LI pin, pull-down
––
3.8 –
150 300
100 200
CI and SDI Pins Logic Input Current
Output Dot Correction Error
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
SWITCHING CHARACTERISTICS
IIN
TJTSD
TJhys
VIN = 0 to 5 V
REXT = 5 kΩ; LSB
Temperature increasing
–20 –
– ±1
– 165
– 15
Clock Hold Time
Data Setup Time
Data Hold Time
Latch Setup Time3
Latch Hold Time
Output Enable Set Up Time
Output Enable Falling to Outputs Turning ON
Propagation Delay Time
tH(CLK)
tSU(D)
tH(D)
tSU(LI)
tH(LI)
tSU(OE)
tP(OE)2
20 –
20 –
20 –
20 –
20 –
40 –
– 200
Clock to Output Propagation Delay Time
Logic Output Fall Time
Logic Output Rise Time
Output Fall Time (Turn Off)
Output Rise Time (Turn On)
Clock Falling Edge to Serial Data Out
Propagation Delay Time
tP(OUT)
tBF
tBR
tf
tr
tP(SDO)
VDS = 1.0 V, IOUT = 150 mA
COB = 50 pF, 4.5 to 0.5 V
COB = 50 pF, 0.5 to 4.5 V
CO = 10 pF, 90% to 10% of IOUT = 10 mA
CO = 10 pF, 90% to 10% of IOUT = 150 mA
CO = 10 pF, 10% to 90% of IOUT = 10 mA
CO = 10 pF, 10% to 90% of IOUT = 150 mA
– 200
– 50
– 30
– 10
– 10
– 50
– 100
– 50
Output Enable In to Output Enable Out
Propagation Delay
tP(OE)
– 50
Latch In to Latch Out Propagation Delay
tP(LE)
– 50
Clock In to Clock Out Propagation Delay
tP(CLK)
– 50
Clock Out Pulse Duration
tw(CLK)
70 100
Maximum CLKIN Frequency
fCLKIN
––
1If VIN is a 4.75 to 5.5 V supply, connect VIN to VREG externally
2Err = [IOUT(min or max) – IOUT(av)] / IOUT(av), where IOUT(av) is the average of 3 output current values.
3In daisy-chained applications, tSU(LI) must be increased for the quantity of pixels in the chain (see Application Information section).
Max. Units
5.0 mA
15.0 mA
17 V
4.5 V
4.0 V
5.4 V
165 mA
57 mA
7%
3.0 V
±3 %/V
1.0 μA
–V
0.8 V
– mV
0.4 V
–V
600 kΩ
400 kΩ
20 μA
– bit
– °C
– °C
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
100 ns
60 ns
– ns
– ns
– ns
– ns
100 ns
100 ns
100 ns
100 ns
130 ns
6 MHz
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
5 Page 
A6280
3-Channel Constant-Current LED Driver
with Programmable PWM Control
Application Information
Timing Considerations
A6280s can be used in large numbers to drive many LEDs with
the control signals connected serially together, with short cables
between each pixel (see figure 8). Because the clock negative
edge drives the data to the SDO (Serial Data Out) pin, and the
CO pin is driven by a 100 ns one-shot function, the clock and
data signals remain synchronized with each other as you move
from the first pixel in the chain to the last.
After all of the data is written to each A6280 in the chain, the
data is latched into each A6280 via a low-to-high transition on
the LI pin. The LO pin of pixel #1 drives the LI pin of pixel #2,
and so on down the chain. These signals are buffered and are
driven asynchronously relative to the CI and SDI pins. Therefore
the mismatch in delays between CO and LO must be taken into
consideration.
Although the mismatches in delays are quite small, they must be
considered when creating the timing pattern for driving the chain.
The key parameter is the setup time from the last CI clock rising
edge to the rising edge of LI.
The minimum A6280 setup time from CI to LI is 20 ns. There
may be a 5 ns per pixel mismatch in the propagation delays of the
CI and LI signals (the delay from CI to CO compared to the delay
from LI to LO). As a rule of thumb, use a setup time, tsu , at the
first A6280 in the chain as calculated below:
tsu = 20 ns + n × 5 ns ,
where n is the number of pixels in the chain.
This will ensure that the setup time at the last pixel in the chain is
at least 20 ns.
CI(1)
CO(1) = CI(2)
CO(2) = CI(3)
CO(n-1) = CI(n)
LI (1)
LO(1) = LI (2)
LO(2) = LI (3)
LO(n-1) = LI (n)
tsu
CI(1) to CI(n)
LI(1) to LI(n)
Figure 7. Signal Delay Mismatch Timing Diagram. tsu is the setup time for signals (CI to
LI) applied to the first pixel in the chain. Note the difference in delay for CI(1) to CI(n)
compared to the delay for LI(1) to LI(n). This must be compensated by increasing tsu.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet A6280.PDF ] | |
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