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PDF A3931 Data sheet ( Hoja de datos )
| Número de pieza | A3931 | |
| Descripción | (A3930 / A3931) Automotive 3-Phase BLDC Controller and MOSFET Driver | |
| Fabricantes | Allegro MicroSystems | |
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A3930 and A3931
Automotive 3-Phase BLDC Controller and MOSFET Driver
Features and Benefits
▪ High current 3-phase gate drive for N-channel MOSFETs
▪ Synchronous rectification
▪ Cross-conduction protection
▪ Charge pump and top-off charge pump for 100% PWM
▪ Integrated commutation decoder logic
▪ Operation over 5.5 to 50 V supply voltage range
▪ Extensive diagnostics output
▪ Provides +5 V Hall sensor power
▪ Low-current sleep mode
Package: 48 Lead LQFP with exposed
thermal pad (suffix JP)
Description
TheA3930 andA3931 are 3-phase brushless dc (BLDC) motor
controllers for use with N-channel external power MOSFETs.
They incorporate much of the circuitry required to design a
cost effective three-phase motor drive system, and have been
specifically designed for automotive applications.
A key automotive requirement is functionality over a wide
input supply range. A unique charge pump regulator provides
adequate (>10V) gate drive for battery voltages down to 7V,
and allows the device to operate with a reduced gate drive at
battery voltages down to 5.5V. Power dissipation in the charge
pump is minimized by switching from a voltage doubling mode
at low supply voltage to a dropout mode at the nominal running
voltage of 14V.
A bootstrap capacitor is used to provide the above-battery
supply voltage required for N-channel MOSFETs. An internal
charge pump for the high-side drive allows for dc (100% duty
cycle) operation.
Internal fixed-frequency PWM current control circuitry can
be used to regulate the maximum load current. The peak
load current limit is set by the selection of an input reference
voltage and external sensing resistor. The PWM frequency is
set by a user-selected external RC timing network. For added
flexibility, the PWM input can be used to provide speed and
Continued on the next page…
Typical Application
3930-DS
Preliminary Data Sheet Subject to Change Without Notice April 6, 2006
1 page  
A3930 and
A3931
Automotive 3-Phase BLDC Controller
and MOSFET Driver
ELECTRICAL CHARACTERISTICS at TJ = –40°C to 150°C, VBB = 7 to 45 V, unless otherwise noted1
Characteristics
Symbol
Test Conditions
Min.
Logic Inputs and Outputs
FFx Fault Output (Open Drain)
FFx Fault Output Leakage Current2
TACHO and DIRO Output High Voltage
TACHO and DIRO Output Low Voltage
Input Low Voltage
Input High Voltage (Except RESET)
RESET Input High Voltage
Input Hysteresis
Input Current (Except H1, H2, H3, and
RESET)2
VOL
IOH
VOH
VOL
VIL
VIH
VIHR
VIHys
IIN
IOL = 1 mA, fault asserted
VO = 5 V, fault not asserted
IOH = –1 mA
IOL = 1 mA
–
–1
V5 – 1 V
–
–
2
2.2
300
–1
RESET Input Pull-Down Resistor
Hx Input Pull-Up Resistor
RPD
RPU
VIN = 5 V
VIN = 0 V
–
–
Current Sense Differential Amplifier
Input Bias Current2
Input Offset Current2
CSP Input Resistance
CSN Input Resistance
Differential Input Voltage
IIBS
IIOS
RCSP
RCSN
VID
CSP = CSN = 0 V
CSP = CSN = 0 V
Measured with respect to AGND
Measured with respect to AGND
VID = CSP – CSN, –1.3 V < CSP < 4 V,
–1.3 V < CSN < 4 V
–95
–20
–
–
0
Output Offset Voltage
Output Offset Voltage Drift
Input Common Mode Range
Differential Input Voltage Gain
Low Output Voltage Error
DC Common Mode Gain
Source Resistance
Output Dynamic Range
Output Current – Sink
Output Current – Source2
Supply Rejection
VOOS
CSP = CSN = 0 V
VOOS(Δt) CSP = CSN = 0 V
VCM CSP = CSN
AV 40 mV < VID < 175 mV, VCM in range
Verr
0 < VID < 40 mV,
VCSOUT = (19 × VID) + VOOS + Verr
ACMdc CSP = CSN = 200 mV
rCSOUT VCSOUT = 2.0 V, ICSOUT = [TBD] μA
VCSOUT –100 μA < ICSOUT < 100 μA
ICSOUT(sink) VCSOUT= 2 V ±5%
ICSOUT(source) VCSOUT= 2 V ±5%
PSRR CSP = CSN = AGND, 0 to 300 kHz
150
–
–1.5
18.2
–20
–
–
0.1
–
–
–
Small Signal 3dB Bandwidth Frequency
Settling Time
f3dB
tSETTLE
VID=10 mVpp
To within 10%, VCSOUT = 1 Vpp square
wave
–
–
Typ.
–
–
–
–
–
–
–
500
–
50
100
–145
–
80
4
–
375
100
–
19
–
–30
30
–
1
–19
45
1.6
400
Max. Units
0.4 V
1 μA
–V
0.4 V
0.8 V
–V
–V
– mV
1 μA
– kΩ
– kΩ
–205
20
–
–
μA
μA
kΩ
kΩ
200 mV
600 mV
– μV/°C
4V
19.4 V/V
20 mV
– dB
–Ω
4.8 V
– mA
– mA
– dB
– MHz
– ns
Continued on the next page…
Preliminary Data Sheet
Subject to Change Without Notice
April 6, 2006
Allegro MicroSystems, Inc.
5
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5 Page 
A3930 and
A3931
Automotive 3-Phase BLDC Controller
and MOSFET Driver
In some circumstances, it may be desirable to completely disable
the internal PWM control. This can be done by pulling the RC
pin directly to AGND. This will disable the internal PWM oscil-
lator and ensure that the output of the PWM latch is always high.
Blank Time When the source driver is turned on, a current spike
occurs due to the reverse-recovery currents of the clamp diodes
and switching transients related to distributed capacitance in the
load. To prevent this current spike from erroneously resetting
the source enable latch, the current-control comparator output
is blanked for a short period of time, tBLANK, when the source
driver is turned on.
The length of tBLANK is different for internal versus external
PWM. It is set by the value of the timing capacitor, CT, according
to the following formulas:
for internal PWM: tBLANK (μs) = 1260 × CT (μF), and
for external PWM: tBLANK (μs) = 2000 × CT (μF) .
A nominal CT value of 680 pF yields a tBLANK of 1.3 μs for
external PWM, and 860 ns for internal PWM. The user must
ensure that CT is large enough to cover the current spike duration
when using the internal sense amplifier.
Diagnostics
Several diagnostic features integrated into the A3930/A3931
provide speed and direction feedback and indications of fault
conditions.
TACHO and DIRO These outputs provide speed and direction
information based on the HE inputs from the motor. As shown in
figure 1, at each commutation point, the TACHO output changes
state independent of motor direction. The DIRO output is updated
at each commutation point to show the motor direction. When
the motor is rotating in the “forward” or positive direction, DIRO
will be high. When rotation is in the “reverse” or negative direc-
tion, DIRO will be low. The actual direction of rotation is deter-
mined from the sequence of the three Hall inputs, Hx. Forward
is when the sequence follows table 3 top-to-bottom and reverse
when the sequence follows table 3 bottom-to-top.
DIRO
TACHO
Commutation
Points
"Forward" Motor Rotation
"Reverse" Motor Rotation
Figure 1. Direction Indication Outputs
Note that there are some circumstances in which the direction
reported on the DIRO output pin and the direction demanded
on the DIR input pin may not be the same. This may happen if
the motor and load have reasonably high inertia. In this case,
changing the state of the DIR pin will cause the torque to reverse,
braking the motor. During this braking, the direction indicated on
the DIRO output will not change.
ESF The state of the enable stop on fault (ESF) pin will deter-
mine the action taken when a short is detected. For other fault
conditions, the action is defined by the type of fault. The action
taken follows the states shown in table 2.
When ESF = 1, any short fault condition will disable all the
gate drive outputs and coast the motor. This disabled state will
be latched until the next phase commutation or until COAST or
RESET go low.
When ESF = 0, under most conditions, although the fault flags,
FF1 and FF2, are still activated, the A3930/A3931will not disrupt
normal operation and will therefore not protect the motor or the
drive circuit from damage. It is imperative that the master control
circuit or an external circuit take any necessary action when a
fault occurs, to prevent damage to components.
If desired, the active low COAST input can be used as a crude
disable circuit by connecting the fault flags FF1 and FF2 to the
COAST input and a pull-up resistor to V5.
FF1, FF2, and VDSTH Fault conditions are indicated by the
state of two open drain output fault flags, FF1 and FF2, as shown
in table 1. In addition to internal temperature, voltage, and logic
monitoring, the A3930/A3931 monitors the state of the external
MOSFETs and the motor current to determine if short circuit
faults occur or a low load condition exists. In the event that two
or more faults are detected simultaneously, the state of the fault
flags will be determined by a logical AND of the fault states of
each flag.
• Undervoltage VREG supplies the low-side gate driver and the
bootstrap charge current. It is critical to ensure that the voltages
are sufficiently high before enabling any of the outputs. The
undervoltage circuit is active during power-up, and will pull
both fault flags low and coast the motor (all gate drives low)
until VREG is greater than approximately 8 V. Note that this is
sufficient to turn on the external power FETs at a battery voltage
as low as 5.5 V, but will not normally provide the rated on-resis-
tance of the FET. This could lead to excessive power dissipation
in the external FET.
Preliminary Data Sheet
Subject to Change Without Notice
April 6, 2006
Allegro MicroSystems, Inc.
11
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet A3931.PDF ] | |
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