PDF EP504 Data sheet ( Hoja de datos )

Número de pieza	EP504
Descripción	AHB Bus to SDRAM Controller
Fabricantes	Eureka
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No Preview Available ! www.DataSheet4U.com Eureka Technology FEATURES EP504 AHB Bus to SDRAM Controller Product Summary • SDRAM controller interfaces directly with AHB Bus and user interface. • Built-in arbitration between two access ports. • Second access port allows memory sharing with user logic devices. • Dual write buffer for simultaneous write posting and SDRAM access. • Dedicated read buffer with data width matching. • Early burst termination and CPU master busy on the AHB bus are supported. • Supports AHB bus data width of 8, 16 and 32 bits. • Zero wait state burst data transfer on both AHB interface and SDRAM. • Operates on both discrete SDRAM chips and PC100/133 SDRAM DIMM. • Supports industrial standard SDRAM from 64Mbit to 256Mbit device sizes. • Pipeline access allows continuous data transfer without wasted cycle. • Fast page access on row address matching. • Independent row address matching for each of the 4 SDRAM banks. • Programmable memory size: 4, 8, 16 and 32 bits per SDRAM. • Programmable SDRAM access timing parameters. • Automatic refresh generation with programmable refresh intervals. • Optimized for ASIC and PLD implementations, including Excalibur PLD. BLOCK DIAGRAM AHB Bus AHB Interface Addr AHB data buffers Arbiter EP504 Address multiplexor Pipeline control Page hit circuit SDRAM or SDRAM DIMM User Interface Control registers Programma- ble timers © 2001 by Eureka Technology Inc. 4962 El Camino Real, Los Altos, CA 94022, USA Tel: 1 650 960 3800 Fax: 1 650 960 3805 http://www.eurekatech.com 1 page

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