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C8051F342 Schematic ( PDF Datasheet ) - Silicon Laboratories

Teilenummer C8051F342
Beschreibung Full Speed USB Flash MCU
Hersteller Silicon Laboratories
Logo Silicon Laboratories Logo 




Gesamt 30 Seiten
C8051F342 Datasheet, Funktion
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Full Speed USB Flash MCU Family
Analog Peripherals
- 10-Bit ADC (C8051F340/1/2/3/4/5/6/7/A/B only)
Up to 200 ksps
Built-in analog multiplexer with single-ended and
differential mode
VREF from external pin, internal reference, or VDD
Built-in temperature sensor
External conversion start input option
- Two comparators
- Internal voltage reference
(C8051F340/1/2/3/4/5/6/7/A/B only)
- Brown-out detector and POR Circuitry
USB Function Controller
- USB specification 2.0 compliant
- Full speed (12 Mbps) or low speed (1.5 Mbps) operation
- Integrated clock recovery; no external crystal required for
full speed or low speed
- Supports eight flexible endpoints
- 1 kB USB buffer memory
- Integrated transceiver; no external resistors required
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-intru-
sive in-system debug (No emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Voltage Supply Input: 2.7 to 5.25 V
- Voltages from 3.6 to 5.25 V supported using On-Chip
Voltage Regulator
HIgh Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
Instructions in 1 or 2 system clocks
- 48 MIPS and 25 MIPS versions available.
- Expanded interrupt handler
Memory
- 4352 or 2304 Bytes RAM
- 64 or 32 kB Flash; In-system programmable in 512-byte
sectors
Digital Peripherals
- 40/25 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced SPI™, SMBus™, and one or two
enhanced UART serial ports
- Four general purpose 16-bit counter/timers
- 16-bit programmable counter array (PCA) with five cap-
ture/compare modules
- External Memory Interface (EMIF)
Clock Sources
- Internal Oscillator: ±0.25% accuracy with clock recovery
enabled. Supports all USB and UART modes
- External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin
modes)
- Low Frequency (80 kHz) Internal Oscillator
- Can switch between clock sources on-the-fly
Packages
- 48-pin TQFP (C8051F340/1/4/5/8/C)
- 32-pin LQFP (C8051F342/3/6/7/9/A/B/D)
- 5x5 mm 32-pin QFN (C8051F342/3/6/7/9/A/B)
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
A 10-bit +
M
U
200 ksps
+
-
X ADC -
TEMP
SENSOR
VREF
VREG
C8051F340/1/2/34/5/6/7/A/B Only
PRECISION INTERNAL
OSCILLATORS
DIGITAL I/O
UART0
UART1*
SPI
SMBus
PCA
Port 0
Port 1
Port 2
4 Timers
Port 3
48 Pin Only
Port 4
* C8051F340/1/4/5/8/A/B/C Only
USB Controller /
Transceiver
HIGH-SPEED CONTROLLER CORE
64/32 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(48/25 MIPS)
DEBUG
CIRCUITRY
4/2 kB RAM
POR WDT
Rev. 1.4 9/09
Copyright © 2009 by Silicon Laboratories
C8051F34x






C8051F342 Datasheet, Funktion
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
17.5.3.Slave Receiver Mode ............................................................................. 201
17.5.4.Slave Transmitter Mode ......................................................................... 202
17.6.SMBus Status Decoding................................................................................. 202
18. UART0.................................................................................................................... 205
18.1.Enhanced Baud Rate Generation................................................................... 206
18.2.Operational Modes ......................................................................................... 206
18.2.1.8-Bit UART ............................................................................................. 207
18.2.2.9-Bit UART ............................................................................................. 208
18.3.Multiprocessor Communications .................................................................... 208
19. UART1 (C8051F340/1/4/5/8/A/B/C Only).............................................................. 213
19.1.Baud Rate Generator ..................................................................................... 214
19.2.Data Format.................................................................................................... 215
19.3.Configuration and Operation .......................................................................... 216
19.3.1.Data Transmission ................................................................................. 216
19.3.2.Data Reception ...................................................................................... 216
19.3.3.Multiprocessor Communications ............................................................ 217
20. Enhanced Serial Peripheral Interface (SPI0)...................................................... 222
20.1.Signal Descriptions......................................................................................... 223
20.1.1.Master Out, Slave In (MOSI).................................................................. 223
20.1.2.Master In, Slave Out (MISO).................................................................. 223
20.1.3.Serial Clock (SCK) ................................................................................. 223
20.1.4.Slave Select (NSS) ................................................................................ 223
20.2.SPI0 Master Mode Operation ......................................................................... 224
20.3.SPI0 Slave Mode Operation ........................................................................... 226
20.4.SPI0 Interrupt Sources ................................................................................... 226
20.5.Serial Clock Timing......................................................................................... 227
20.6.SPI Special Function Registers ...................................................................... 229
21. Timers.................................................................................................................... 235
21.1.Timer 0 and Timer 1 ....................................................................................... 235
21.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 235
21.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 236
21.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 237
21.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 238
21.2.Timer 2 .......................................................................................................... 243
21.2.1.16-bit Timer with Auto-Reload................................................................ 243
21.2.2.8-bit Timers with Auto-Reload................................................................ 244
21.2.3.Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge ...... 245
21.3.Timer 3 .......................................................................................................... 249
21.3.1.16-bit Timer with Auto-Reload................................................................ 249
21.3.2.8-bit Timers with Auto-Reload................................................................ 250
21.3.3.USB Start-of-Frame Capture.................................................................. 251
22. Programmable Counter Array (PCA0) ................................................................ 255
22.1.PCA Counter/Timer ........................................................................................ 256
22.2.Capture/Compare Modules ............................................................................ 257
22.2.1.Edge-triggered Capture Mode................................................................ 258
6 Rev. 1.3

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C8051F342 pdf, datenblatt
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
11 Rev. 1.3

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