Datenblatt-pdf.com


W83194BR-648 Schematic ( PDF Datasheet ) - Winbond

Teilenummer W83194BR-648
Beschreibung CLOCK GENERATOR
Hersteller Winbond
Logo Winbond Logo 




Gesamt 26 Seiten
W83194BR-648 Datasheet, Funktion
www.DataSheet4U.com
W83194BR-648
Data Sheet
WIBOND
CLOCK GENERATOR
FOR
SIS P4 SERIES CHIPSET
Publication Release Date: April 13, 2005
- I - Revision 1.1






W83194BR-648 Datasheet, Funktion
W83194BR-648
3. PIN CONFIGURATION
VDDR
F S 0 & /R E F 0
F S 1 & /R E F 1
F S 2 & /R E F 2
GND
X IN
XO U T
GND
Z C LK 0
Z C LK 1
VDDZ
P C I_ S T O P # *
VDDPCI
F S 3 & /P C IC L K _ F 0
F S 4 & /P C IC L K _ F 1
P C IC L K 0
P C IC L K 1
GND
VDDPCI
P C IC L K 2
P C IC L K 3
P C IC L K 4
P C IC L K 5
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
#: Active low
*: Internal pull up resistor 120K to VDD
&: Internal Pull-down resistor 120K to GND
48 VDDSD
47 SDRAM
46 G ND
45 CPU_STO P#*
44 C PUC LKT_1
43 CPUCLKC_1
42 VDDC
41 G ND
40 C PUC LKT_0
39 CPUCLKC_0
3 8 IR E F
37 G ND
36 VDDA
35 SDCLK*
34 SDATA*
3 3 P D # */V T T _ P W G D
32 G ND
31 AG PCLK0
30 AG PCLK1
29 VDDAG P
28 VDD48
27 48M Hz
2 6 2 4 _ 4 8 M H z /M U L T IS E L 0 *
25 G ND
4. BLOCK DIAGRAM
XIN
XOUT
VTT_PWGD
FS<0:4>
PD#*
PCI_STOP#*
CPU_STOP#*
MULTISEL0*
SDATA*
SDCLK*
PLL2
XTAL
OSC
PLL1
Spread
Spectrum
M/N/Ratio
S.S.P
ROM
Latch
&
POR
Control
Logic
&
Config
Register
I2C
interface
Driver
1/2 Mux
VCOCLK
Divider
Stop
Stop
48MHz
24_48MHz
3
REF0:2
3
CPUCLK_T 0:1
CPUCLK_C 0:1
3
SDRAM
2
ZCLK 0:1
2
AGPCLK 0:1
8 PCICLK_F0:1
PCICLK_0:5
Rref
-2-

6 Page









W83194BR-648 pdf, datenblatt
W83194BR-648
7.3 Register 6 PCI Clock (1 = Enable, 0 = Stopped) (Default = FFH)
BIT PIN NO PWD
DESCRIPTION
7 15 1 PCICLK_F1 output control
6 14 1 PCICLK_F0 output control
5 23 1 PCICLK 5 output control
4 22 1 PCICLK 4 output control
3 21 1 PCICLK 3 output control
2 20 1 PCICLK 2 output control
1 17 1 PCICLK 1 output control
0 16 1 PCICLK 0 output control
7.4 Register 7 48 MHz, ZCLK, REF Clock (1 = Enable, 0 = Stopped) (Default = FFH)
BIT PIN NO PWD
DESCRIPTION
7 27 1 48 MHZ output control
6 26 1 24_48 MHz output control
24/48 MHz frequency control
5 SEL_24 1 1: 24 MHz.
0: 48 MHz.
4 10 1 ZCLK1 output control
3 9 1 ZCLK0 output control
2 4 1 REF2 output control
1 3 1 REF1 output control
0 2 1 REF0 output control
7.5 Register 8: AGP Control (1 = Enable, 0 = Stopped) (Default = CEH)
BIT Pin NO PWD
DESCRIPTION
7
1
CPUCLKT/C0 Stop control: 0: CPUCLK0 free run
1: CPUCLK0 can stopped by CPU_STOP#
6
1
CPUCLKT/C1 Stop control: 0: CPUCLK1 free run
1: CPUCLK1 can stopped by CPU_STOP#
5
0
PCI_F0 Stop control: 0: PCI_F0 free run
1: PCI_F0 can stopped by PCI_STOP#
4
0
PCI_F1 Stop control: 0: PCI_F1 free run
1: PCI_F1 can stopped by PCI_STOP#
3 30 1 AGP_1 output control
2 31 1 AGP_0 output control
1 MULTISEL0 X MULTISEL0 trapping pin data read back, Default 1.
0 Reserved 0 Reserved
-8-

12 Page





SeitenGesamt 26 Seiten
PDF Download[ W83194BR-648 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
W83194BR-640166MHZ CLOCKWinbond
Winbond
W83194BR-645CLOCK GENERATORWinbond
Winbond
W83194BR-648CLOCK GENERATORWinbond
Winbond

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche