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ECP2-xx Schematic ( PDF Datasheet ) - Lattice Semiconductor

Teilenummer ECP2-xx
Beschreibung ECP2/M Family
Hersteller Lattice Semiconductor
Logo Lattice Semiconductor Logo 




Gesamt 30 Seiten
ECP2-xx Datasheet, Funktion
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LatticeECP2/M Family Data Sheet
DS1006 Version 02.2, December 2006






ECP2-xx Datasheet, Funktion
www.DataSheet4U.com
Lattice Semiconductor
Architecture
LatticeECP2/M Family Data Sheet
PFU Blocks
The core of the LatticeECP2/M device consists of PFU blocks which are provided in two forms, the PFU and PFF.
The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF
blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remain-
der of this data sheet will use the term PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnec-
tions to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated with each PFU block.
Figure 2-3. PFU Diagram
From
Routing
LUT4 &
CARRY
LUT4 &
CARRY
Slice 0
DD
FF FF
LUT4 &
CARRY
LUT4 &
CARRY
Slice 1
DD
FF FF
LUT4 &
CARRY
LUT4 &
CARRY
Slice 2
DD
FF FF
LUT4
LUT4
Slice 3
To
Routing
Slice
Slice 0 through Slice 2 contain two LUT4s feeding two registers, whereas Slice 3 contains two LUT4s only. For
PFUs, Slice 0 and Slice 2 can also be configured as distributed memory, a capability not available in the PFF.
Table 2-1 shows the capability of the slices in both PFF and PFU blocks along with the operation modes they
enable. In addition, each PFU contains some logic that allows the LUTs to be combined to perform functions such
as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchro-
nous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the
internal logic of the slice. The registers in the slice can be configured for positive/negative and edge triggered or
level sensitive clocks.
Table 2-1. Resources and Modes Available per Slice
Slice
Slice 0
Slice 1
Slice 2
Slice 3
PFU BLock
PFF Block
Resources
Modes
Resources
Modes
2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM
2 LUT4s and 2 Registers Logic, Ripple, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM
2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM
2 LUT4s
Logic, ROM
2 LUT4s
Logic, ROM
Slices 0, 1 and 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent
slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has 13
input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice 2.
2-3

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ECP2-xx pdf, datenblatt
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Lattice Semiconductor
Architecture
LatticeECP2/M Family Data Sheet
Table 2-5. DLL Signals
Signal
CLKI
CLKFB
RSTN
ALUHOLD
UDDCNTL
DCNTL[8:0]
CLKOP
CLKOS
LOCK
I/O
I
I
I
I
I
O
O
O
O
Description
Clock input from external pin or routing
DLL feed input from DLL output, clock net, routing or external pin
Active low synchronous reset
Active high freezes the ALU
Synchronous enable signal (hold high for two cycles) from routing
Encoded digital control signals for PIC INDEL and slave delay calibration
The primary clock output
The secondary clock output with fine phase shift and/or division by 2 or by 4
Active high phase lock indicator
DLLDELA Delay Block
Closely associated with each DLL is a DLLDELA block. This is a delay block consisting of a delay line with taps and
a selection scheme that selects one of the taps. The DCNTL[8:0] bus controls the delay of the CLKO signal. Typi-
cally this is the delay setting that the DLL uses to achieve phase alignment. This results in the delay providing a cal-
ibrated 90° phase shift that is useful in centering a clock in the middle of a data cycle for source synchronous data.
The CLKO signal feeds the edge clock network. Figure 2-7 shows the connections between the DLL block and the
DLLDELA delay block. For more information, please see details of additional technical documentation at the end of
this data sheet.
Figure 2-7. DLLDELA Delay Block
PLL_PIO
Routing
Routing
DLL_PIO
CLKFB_CK
CLKOP
GDLLFB_PIO
ECLK1
* CLKI
* CLKFB
DLL Block
DCNTL[8:0]
* CLKI DLLDELA Delay Block
CLKOP
CLKOS
LOCK
CLKO
* Software selectable
PLL/DLL Cascading
LatticeECP2/M devices have been designed to allow certain combinations of PLL (GPLL and SPLL) and DLL cas-
cading. The allowable combinations are as follows:
• PLL to PLL supported
• PLL to DLL supported
2-9

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