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PDF PLUS153B Data sheet ( Hoja de datos )
| Número de pieza | PLUS153B | |
| Descripción | Programmable logic arrays | |
| Fabricantes | NXP Semiconductors | |
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Philips Semiconductors Programmable Logic Devices
Programmable logic arrays
(18 × 42 × 10)
Product specification
PLUS153B/D
DESCRIPTION
The PLUS153 PLDs are high speed,
combinatorial Programmable Logic Arrays.
The Philips Semiconductors state-of-the-art
Oxide Isolated Bipolar fabrication process is
employed to produce propagation delays as
short as 12ns.
The 20-pin PLUS153 devices have a
programmable AND array and a
programmable OR array. Unlike PAL®
devices, 100% product term sharing is
supported. Any of the 32 logic product terms
can be connected to any or all of the 10
output OR gates. Most PAL ICs are limited to
7 AND terms per OR function; the PLUS153
devices can support up to 32 input wide OR
functions.
The polarity of each output is
user-programmable as either active-High or
active-Low, thus allowing AND-OR or
AND-NOR logic implementation. This feature
adds an element of design flexibility,
particularly when implementing complex
decoding functions.
The PLUS153 devices are
user-programmable using one of several
commercially available, industry standard
PLD programmers.
FEATURES
• I/O propagation delays (worst case)
– PLUS153B – 15ns max.
– PLUS153D – 12ns max.
• Functional superset of 16L8 and most
other 20-pin combinatorial PAL devices
• Two programmable arrays
– Supports 32 input wide OR functions
• 8 inputs
• 10 bi-directional I/O
• 42 AND gates
– 32 logic product terms
– 10 direction control terms
• Programmable output polarity
– Active-High or Active-Low
• Security fuse
• 3-State outputs
• Power dissipation: 750mW (typ.)
• TTL Compatible
APPLICATIONS
• Random logic
• Code converters
• Fault detectors
• Function generators
• Address mapping
• Multiplexing
PIN CONFIGURATIONS
N Package
I0 1
I1 2
I2 3
I3 4
I4 5
I5 6
I6 7
I7 8
B0 9
GND 10
20 VCC
19 B9
18 B8
17 B7
16 B6
15 B5
14 B4
13 B3
12 B2
11 B1
N = Plastic Dual In-Line Package (300mil-wide)
A Package
I2 I1 I0 VCC B9
3 2 1 20 19
I3 4
18 B8
I4 5
17 B7
I5 6
16 B6
I6 7
15 B5
I7 8
14 B4
9 10 11 12 13
B0 GND B1 B2 B3
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION
20-Pin Plastic Dual-In-Line 300mil-wide
20-Pin Plastic Dual-In-Line 300mil-wide
20-Pin Plastic Leaded Chip Carrier
20-Pin Plastic Leaded Chip Carrier
tPD (MAX)
15ns
12ns
15ns
12ns
ORDER CODE
PLUS153BN
PLUS153DN
PLUS153BA
PLUS153DA
DRAWING NUMBER
0408D
0408D
0400E
0400E
®PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices Corporation.
October 22, 1993
9
853–1285 11164
1 page  
Philips Semiconductors Programmable Logic Devices
Programmable logic arrays
(18 × 42 × 10)
Product specification
PLUS153B/D
AC ELECTRICAL CHARACTERISTICS
0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V, R1 = 300Ω, R2 = 390Ω
LIMITS
SYMBOL PARAMETER
FROM
TO
TEST
PLUS153B
PLUS153D
UNIT
CONDITION MIN TYP MAX MIN TYP MAX
tPD Propagation Delay2 Input +/– Output +/– CL = 30pF
11 15
10 12
ns
tOE Output Enable1
Input +/– Output – CL = 30pF
11 15
10 12
ns
tOD Output Disable1
Input +/–
Output +
CL = 5pF
11 15
10 12
ns
NOTES:
1. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output
voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed.
2. All propagation delays are measured and specified under worst case conditions.
VOLTAGE WAVEFORMS
+3.0V
90%
0V
+3.0V
10%
5ns
tR tF
5ns
90%
0V
5ns
10%
5ns
MEASUREMENTS:
All circuit delays are measured at the +1.5V level
of inputs and outputs, unless otherwise specified.
Input Pulses
TEST LOAD CIRCUIT
C1 C2
INPUTS
NOTE:
C1 and C2 are to bypass VCC to GND.
VCC +5V S1
I0 BY
I7 DUT
BW
BX GND BZ
R1
R2 CL
OUTPUTS
TIMING DEFINITIONS
SYMBOL
PARAMETER
tPD Propagation delay between
input and output.
tOD Delay between input change
and when output is off (Hi-Z
or High).
tOE Delay between input change
and when output reflects
specified output level.
TIMING DIAGRAM
I, B 1.5V
B 1.5V
tPD
1.5V
1.5V
+3V
0V
VOH
VT 1.5V
VOL
tOD tOE
October 22, 1993
13
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet PLUS153B.PDF ] | |
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