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PDF PI6C48533-01 Data sheet ( Hoja de datos )
| Número de pieza | PI6C48533-01 | |
| Descripción | Differential/LVCMOS to LVPECL Fanout Buffer | |
| Fabricantes | Pericom Semiconductor | |
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PI6C48533-01
3.3V Low Skew 1-to-4
Differential/LVCMOS to LVPECL Fanout Buffer
Features
• Pin-to-pin compatible to ICS8533-01
• Maximum operation frequency: 800MHz
• 4 pair of differential LVPECL outputs
• Selectable differential CLK and PCLK inputs
• CLK, nCLK pair accepts LVDS, LVPECL, LVHSTL,
SSTL and HCSL input level
• PCLK, nPCLK pair supports LVPECL, CML and SSTL
input level
• Output Skew: 100ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 2ns (maximum)
• 3.3V power supply
• Operating Temperature: -40oC to 85oC
• Packaging (Pb-free & Green avaliable):
-20-pin TSSOP (L)
Description
The PI6C48533-01 is a high-performance low-skew LVPECLfanout
buffer. PI6C48533-01 features two selectable differential inputs and
translates to four LVPECL ultra-low jitter outputs. The inputs can
also be configured to single-ended with external resistor bias circuit.
The CLK input accepts LPECL or LVDS or LVHSTL or SSTL or
HCSL signals, and PCLK input accepts LVPECL or SSTL or CML
signals. The outputs are synchronized with input clock during asyn-
chronous assertion/deassertion of CLK_EN pin. PI6C48533-01 is
ideal for differential to LVPECL translations and/or LVPECL clock
distribution. Typical clock translation and distribution applications
are data-communications and telecommunications.
Block Diagram
CLK_EN
CLK
nCLK
PCLK
nPCLK
D
Q
LE
0
1
CLK_SEL
Pin Diagram
VEE 1
CLK_EN 2
CLK_SEL 3
CLK 4
Q0 nCLK 5
nQ0 PCLK 6
Q1 nPCLK 7
nQ1 NC 8
NC 9
Q2
nQ2
VCC 10
Q3
nQ3
20 Q0
19 nQ0
18 VCC
17 Q1
16 nQ1
15 Q2
14 nQ2
13 VCC
12 Q3
11 nQ3
1
PS8737B
02/08/06
1 page  
PI6C48533-01
3.3V Low Skew 1-to-4
Differential/LVCMOS to LVPECL Fanout Buffer
LVPECL DC Characteristics
(TA = -40oC to 85oC, VCC = 3.0V to 3.6V, RL= 50Ω to VCC - 2V, unless otherwise stated below.)
Symbol
Parameter
Conditions
Min.
IIH
Input High
Current
nCLK, nPCLK
CLK, PCLK
VIN = VCC = 3.6V
VIN = VCC = 3.6V
IIL
Input Low
Current
nCLK, nPCLK
CLK, PCLK
VCC = 3.6V, VIN = 0V
VCC = 3.6V, VIN = 0V
-150
-5
VPP Peak-to-peak Voltage
0.3
VCMR Common Mode Input Voltage; Note(1,2)
VEE+1.5
VOH Output High Voltage
VCC-1.4
VOL Output Low Voltage
VCC-2.0
VSWING Peak-to-peak Output Voltage Swing
0.6
Notes:
1. For single ended applications, the maximum input voltage for PCLK and nPCLK is VCC+0.3V.
2. Common mode voltage is defined as VIH.
Typ. Max.
5
150
1
VCC
VCC-0.9
VCC-1.6
1.0
Units
µA
V
AC Characteristics(1) (TA = -40oC to 85oC, VCC = 3.0V to 3.6V, RL= 50Ω to VCC - 2V, unless otherwise stated below.)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
fmax
tPd
Tsk(o)
Tsk(pp)
Output Frequency
Propagation Delay(2)
Output-to-output Skew(3)
Part-to-part Skew(4)
500 800 MHz
1.0 2.0 ns
100
150 ps
tr/tf Output Rise/Fall time
20% - 80%
75
300
odc Output duty cycle
40 60 %
Notes:
1. All parameters are measured at 500MHz unless noted otherwise
2. Measured from the VCC/2 of the input to the differential output crossing point
3 Defined as skew between outputs at the same supply voltage and with equal load condition. Measured at the outputs differential crossing
point.
4. Defined as skew between outputs on different parts operating at the same supply voltage and with equal load condition. Measured at the
outputs differential crossing point.
5
PS8737B
02/08/06
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PI6C48533-01.PDF ] | |
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