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PDF GLT44016 Data sheet ( Hoja de datos )
| Número de pieza | GLT44016 | |
| Descripción | 256K X 16 CMOS DYNAMIC RAM | |
| Fabricantes | G-Link | |
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GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Features :
∗ 262,144 words by 16 bits organization.
∗ Fast access time and cycle time.
∗ Dual CAS Input.
∗ Low power dissipation.
∗ Read-Modify-Write, RAS -Only Refresh,
CAS -Before-RAS Refresh, Hidden
Refresh and Test Mode Capability.
∗ 512 refresh cycles per 8ms.
∗ Available in 40-Pin 400 mil SOJ and 40/44
Pin TSOP(II)
∗ Single 5.0V±10% Power Supply.
∗ All inputs and Outputs are TTL
compatible.
∗ Extended Data-Out(EDO) Page Mode
operation.
Description :
The GLT44016 is a 262,144 x 16 bit
high-performance CMOS dynamic random
access memory. The GLT44016 offers Fast
Page mode with Extended Data Output, and
has both BYTE WRITE and WORD WRITE
access cycles via two CAS pins. The
GLT44016 has symmetric address and
accepts 512-cycle refresh in 8ms interval.
All inputs are TTL compatible. EDO
Page Mode operation allows random access
up to 512 x 16 bits within a page, with cycle
times as short as 10ns.
The GLT44016 is best suited for
graphics, and DSP applications requiring
high performance memories.
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC)
25 28 30 35 40 50
25 ns 28 ns 30 ns 35 ns 40 ns 50 ns
Max. Column Address Access Time, (tCAA)
13 ns 13 ns 16 ns 18 ns 20 ns 25 ns
Min. Extended Data Out Page Mode Cycle Time, (tPC) 10 ns 10 ns 12 ns 13 ns 15 ns 20 ns
Min. Read/Write Cycle Time, (tRC)
45 ns 45 ns 60 ns 65 ns 70 ns 85 ns
Max. CAS Access Time (tCAC)
8 ns 8 ns 10 ns 11 ns 12 ns 14 ns
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
-1-
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
1 page  
G-LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC=5V±10%, VSS=0V, unless otherwise specified.
Sym.
Parameter
ILI Input Leakage Current
(any input pin)
ILO Output Leakage Current
(for High-Z State)
ICC1 Operating Current,
Random READ/WRITE
ICC2 Standby Current,(TTL)
ICC3 Refresh Current,
RAS -Only
ICC4 Operating Current,
EDO Page Mode
ICC5 Refresh Current,
CAS Before RAS
ICC6 Standby Current, (CMOS)
Test Conditions
0V ≤ VIN ≤ 5.5V
(All other pins not under
test=0V)
0V ≤ Vout ≤ 5.5V
Output is disabled (Hiz)
tRC = tRC (min.)
RAS , UCAS , LCAS at VIH
other inputs ≥VSS
RAS cycling, UCAS ,
LCAS at VIH
tRC = tRC (min.)
RAS at VIL, UCAS , LCAS
address cycling:tPC=tPC(min.)
RAS , UCAS , LCAS
address cycling:
tRC=tRC (min.)
RAS ≥VCC-0.2V,
UCAS ≥VCC-0.2V,
Access
Time
tRAC = 25ns
tRAC = 28ns
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 50ns
tRAC = 25ns
tRAC = 28ns
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 50ns
tRAC = 25ns
tRAC = 28ns
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 50ns
tRAC = 25ns
tRAC = 28ns
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 50ns
Min.
-10
-10
Typ
Max. Unit Notes
+10 µA
+10 µA
270
270 mA 1,2
250
210
190
170
4 mA
270
270 mA
2
250
210
190
170
270
270 mA 1,2
250
210
190
170
270 mA
1
270
250
210
190
170
2 mA
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
VOH Output High Voltage
LCAS ≥VCC-0.2V,
All other inputs VSS
IOL = 4.2mA
IOH = -5.0mA
-1
+0.8 V
3
2.4
VCC+1
V
3
0.4 V
2.4 V
Notes:
1.ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output open.
2.ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle in
random Read/Write and EDO Fast Page Mode.
3.Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1.0V for a period not to exceed 20ns. All AC
parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC.
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
-5-
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
5 Page 
G-LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Fast Page Read Cycle
VIH-
RAS
VIL-
VIH-
CAS
VIL-
VIH-
Address
VIL-
VIH-
WE
VIL-
tRASP
tRP
tCRP
tRCD
tCAS
tPC
tCP tCAS
tASR
tRAD
tRAH
tASC
tCSH
tCAH
ROW
ADDR.
COLUMN
ADDRESS
tRCS
tRCH
tASC
tCAH
COLUMN
ADDRESS
tRCS
tPC
tCP tRSH
tCAS
tASC
tCAH
COLUMN
ADDRESS
tRCS
tRCH
tRRH
tCAC
tCAC
VIH-
OE
VIL-
VIH-
DQ
VIL-
tOEA
tRAC
tCLZ
tAA
tAA
tOFF
tOEZ
tCLZ
tOEA
tAA
tOFF tCLZ
tOEZ
tOFF
tOEZ
VALID
DATA-UOT
VALID
DATA-UOT
VALID
DATA-UOT
Fast Page Write Cycle NOTE : DOUT = Open
VIH-
RAS
VIL-
tCRP
tRCD
tPC
tCAS
tCP
tRASP
tPC
tCAS
tRHCP
tCP tRSH
VIH-
CAS
VIL-
VIH-
Address
VIL-
tASR
tRAD
tRAH
tASC
tCSH
tCAH
ROW
ADDR.
COLUMN
ADDRESS
tCAS
tASC
tCAH
COLUMN
ADDRESS
tASC
tCAH
COLUMN
ADDRESS
Don't Care
tRP
tWCS
tWCH
tWCS tWCH
tWCS
tWCH
VIH-
WE
VIL-
VIH-
OE
VIL-
tWP
tCWL
tDS tDH
tWP
tCWL
tWP
tCWL
tRWL
tDS tDS
tDS tDS
VIH-
DQ
VIL-
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
Don't Care
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
- 11 -
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet GLT44016.PDF ] | |
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