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PDF AC104QF Data sheet ( Hoja de datos )
| Número de pieza | AC104QF | |
| Descripción | Ultra Low Power 10/100 Quad RMII Ethernet Transceiver | |
| Fabricantes | Altima | |
| Logotipo |  |
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Altima Communications Inc.
AC104QF
Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
GENERAL DESCRIPTION
The AC104QF is a highly integrated, 3.3V, low
power, four port, 10Base-T/100Base-TX/FX,
Ethernet transceiver implemented in 0.35µm CMOS
technology. Multiple modes of operation including
normal operation, test mode and power saving mode
are available through either hardware or software
control.
Features include MAC interfaces, ENDECs,
Scrambler/Descrambler, and Auto-Negotiation
(ANeg) with support for parallel detection. The
transmitter includes a dual-speed clock synthesizer
that only needs one external clock source. The chip
has built-in wave shaping driver circuit for both
10Mbps and 100Mbps, eliminating the need for an
external hybrid filter. The receiver has an adaptive
equalizer / DC restoration circuit for accurate clock /
data recovery for the 100Base-TX signal. It also
provides an on-chip low pass filer / Squelch circuit
for the 10Base-T signal.
MAC interfaces support four ports of 10/100 RMII.
Media Interfaces support 4 ports of 10/100TX or 3
ports 10/100TX and 1 port 100FX.
FEATURES
• 4 RMII
• RMII 5Volt tolerant and 2.5Volt capable
• 4 10/100 TX or 3 10/100 TX and 1 100 FX
• Full Duplex or Half Duplex
• FEFI on 100FX
• Very small package
• 100PQFP
• Very low power – TYP < 280mW (/ port)
• Cable Detect mode – TYP < 40mW (/ port)
• Power Down mo de – TYP < 3.3mW (/ port)
• Selectable TX drivers for 1:1 or 1.25:1
transformers for additional power reduction
• 3.3Volt .35micron CMOS
• Fully compliant with
• IEEE 802.3 / 802.3u
• RMII
• UNH test labs
• Baseline Wander Compensation
• Multi-Function LED outputs
• Cable length indicator
• Reverse polarity detection and correction with
Register Bit indication – Automatic or Forced
• 8 programmable interrupts
• Diagnostic registers
BLOCK DIAGRAM
Port 0
Port 1
Port 2
Port 3
RMII/MII
Interface
MII SMI
PCS
.Framer
.Carrier Detect
.4B/5B
PMA
.Clock Recov.
.Link Monitor
.Signal Detect
25
MHz
10BASE -T
Control/Status
20
MHz
TP_PMD
100TX
.MLT-3
.BLW
.Stream Cipher
100RX
10TX
10RX
Mux
TXOP/N(3)
RXIP/N(3)
FXTP/N(3)
FXRP/N(3)
RX FLP
MII Serial Management
Interface and Registers
PLLClk Gen.
Test/LED Control
Auto-
25 Negotiation
MHz
PHYAD[4:0]
XTLP/N CKIN TEST[3:0] LED Drivers
TXOP/N(0)
RXIP/N(0)
TXOP/N(1)
RXIP/N(1)
TXOP/N(2)
RXIP/N(2)
1 page  
AC104QF
Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
PIN DIAGRAM - AC104QF
RX_ER(0)
CRS_DV(0)
CGND
TXD[1](0)
TXD[0](0)
TX_EN(0)
OGND
LEDDPX(1) / PHYAD[4]
LEDACT(1) / PHYAD[3]
LEDSPD(1) / PHYAD[2]
LEDDPX(0) / FX_DIS
LEDACT(0)
LEDSPD(0) / TP125
INTR
RST*
GAGND
IBREF
GAVDD
GAVDD
AVDD
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
AC104QF
50 TXD[1](3)
49 CGND
48 CRS_DV(3)
47 RX_ER(3) / PHYAD_ST
46 RXD[0](3)
45 RXD[1](3)
44 OVDD
43 LEDSPD(2) / FORCE100
42 LEDACT(2)
41 LEDDPX(2)
40 LEDSPD(3) / BURN_IN*
39 LEDACT(3) / ANEGA
38 LEDDPX(3) / SCRAM_EN
37 FXTN(3)
36 FXTP(3)
35 FXRN(3) / TST[3]
34 FXRP(3) / TST[2]
33 SDN(3) / TST[1]
32 SDP(3) / TST[0]
31 AVDD
2055 Gateway Parkway Suite 700, San Jose, CA 95110 (408) 453-3700 (www.altimacom.com)
Altima Communications Inc. reserves the right to make changes to this document without notice.
Document Revision 3.2
Page 5 of 37
5 Page 
AC104QF
Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
will assert this bit to a zero. For write operation, the
station will drive a one for the first bit time, and a
zero for the second bit time. The 16 bits data field is
then presented. The first bit that is transmitted is bit
15 of the register content. (See SMI Read/Write
Sequence)
Interrupt
The INTR pin on the Phy will be asserted whenever
one of 8 selectable interrupt events occur. Assertion
state is programmable to either high or low through
the INTR_LEVL register bit. Selection is made by
setting the appropriate bit in the upper half of the
Interrupt Control / Status register. When the INTR
bit goes active, the MAC interface is required to read
the Interrupt Control / Status register to determine
which event caused the interrupt. The Status bits are
read only and clear on read. When INTR is not
asserted, the pin is held in a high impedance state.
Carrier Sense / RX_DV
Carrier sense is asserted asynchronously on the CRS
pins as soon as activity is detected on the receive data
stream. RX_DV is asserted as soon as a valid SSD
(Start-of-Stream Delimiter) is detected. Carrier sense
and RX_DV are de-asserted synchronously upon
detection of a valid end of stream delimiter or two
consecutive idle code groups in the receive data
stream. However, if the carrier sense is asserted and a
valid SSD is not detected immediately, RX_ER is
asserted instead of RX_DV.
Transmit Function
Parallel to Serial logic is used to convert the 2-bit
(RMII) or 4-bit (MII) data into the serial stream. The
serialized data goes directly to the Manchester
encoder where it is synthesized through the output
waveshaping driver. The waveshaper reduces any
EMI emission by filtering out the harmonics,
therefore eliminating the need for an external filter.
Receive Function
The received signal passes through a low-pass filter,
which filters out the noise from the cable, board, and
transformer. This eliminates the need for a 10Base-T
external filter. A Manchester decoder converts the
incoming serial stream. Serial to Parallel logic is
used to generate the 2-bit (RMII) or 4-bit (MII) data.
Link Monitor
The 10-Base-T link-pulse detection circuit will
constantly monitor the RXIP/RXIN pins for the
presence of valid link pulses. In the absence of valid
link pules, the Link Status bit will be cleared and the
Link LED will de-assert.
100BASE-TX
When configured to run in 100Base-TX mode, either
through hardware configuration, software
configuration or ANeg, the Phy will support all the
features and parameters of the industry standards.
In 10Base-T mode, CRS is asserted asynchronously
when the valid preamble and data activity is detected
on the RXIP and RXIN pins.
In the half duplex mode, the CRS is activated during
the transmit and receiving of data. In the full duplex
mode, the CRS is activated during data reception
only.
MEDIA INTERFACE
10BASE-T
When configured to run in 10Base-T mode, either
through hardware configuration, software
configuration or ANeg, the Phy will support all the
features and parameters of the industry standards.
Transmit Function
In 100Base-TX mode, the Phy transmit function
converts synchronous 2-bit (RMII) or 4-bit (MII) data
to a pair of 125 Mbps differential serial data streams.
The serial data is transmitted over network twisted
pair cables via an isolation transformer. Data
conversion includes 4B/5B encoding, scrambling,
parallel to serial, NRZ to NRZI, and MLT-3
encoding. The entire operation is synchronous to 25
MHz and 125 MHz clock. Both clocks are generated
by an on-chip PLL clock synthesizer that is locked on
to an external 25 MHz clock source.
The transmit data is transmitted from the MAC to the
Phy via the TXD[n:0] signals. The 4B/5B encoder
replaces the first two nibbles of the preamble from
the MAC frame with a /J/K/ code-group pair Start-of-
Stream Delimiter (SSD), following the onset of
TX_EN signal. The 4B/5B encoder appends a /T/R/
code-group pair End-of-Stream Delimiter (ESD) to
the end of transmission in place of the first two IDLE
2055 Gateway Parkway Suite 700, San Jose, CA 95110 (408) 453-3700 (www.altimacom.com)
Altima Communications Inc. reserves the right to make changes to this document without notice.
Document Revision 4.0
Page 11 of 37
11 Page | ||
| Páginas | Total 37 Páginas | |
| PDF Descargar | [ Datasheet AC104QF.PDF ] | |
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