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ADC081500 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC081500
Beschreibung A/D Converter
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 28 Seiten
ADC081500 Datasheet, Funktion
www.DataSheet4U.com
September 2005
ADC081500
High Performance, Low Power, 8-Bit, 1.5 GSPS A/D
Converter
General Description
The ADC081500 is a low power, high performance CMOS
analog-to-digital converter that digitizes signals to 8 bits
resolution at sample rates up to 1.7 GSPS. Consuming a
typical 1.2 W at 1.5 GSPS from a single 1.9 Volt supply, this
device is guaranteed to have no missing codes over the full
operating temperature range. The unique folding and inter-
polating architecture, the fully differential comparator design,
the innovative design of the internal sample-and-hold ampli-
fier and the self-calibration scheme enable a very flat re-
sponse of all dynamic parameters beyond Nyquist, produc-
ing a high 7.3 ENOB with a 748 MHz input signal and a 1.5
GHz sample rate while providing a 10-18 B.E.R. Output
formatting is offset binary and the LVDS digital outputs are
compliant with IEEE 1596.3-1996, with the exception of an
adjustable common mode voltage between 0.8V and 1.2V.
The converter output has a 1:2 demultiplexer that feeds two
LVDS buses and reduces the output data rate on each bus to
one-half the sample rate.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40˚C TA +85˚C) temperature range.
Features
n Internal Sample-and-Hold
n Single +1.9V ±0.1V Operation
n Choice of SDR or DDR output clocking
n Multiple ADC Synchronization Capability
n Guaranteed No Missing Codes
n Serial Interface for Extended Control
n Fine Adjustment of Input Full-Scale Range and Offset
n Duty Cycle Corrected Sample Clock
Key Specifications
n Resolution
n Max Conversion Rate
n Bit Error Rate
n ENOB @ 748 MHz Input
n DNL
n Power Consumption
— Operating
— Power Down Mode
8 Bits
1.5 GSPS (min)
10-18 (typ)
7.3 Bits (typ)
±0.15 LSB (typ)
1.2 W (typ)
3.5 mW (typ)
Applications
n Direct RF Down Conversion
n Digital Oscilloscopes
n Satellite Set-top boxes
n Communications Systems
n Test Instrumentation
Block Diagram
© 2005 National Semiconductor Corporation DS201531
20153153
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ADC081500 Datasheet, Funktion
Pin Descriptions and Equivalent Circuits (Continued)
Pin Functions
Pin No.
Symbol
22, 23,
29,
36-39,
43-50,
52,
54-61,
NC
63,
65-72,
75-78,
98, 109,
120
Equivalent Circuit
Description
No Connection. Make no connection to these pins.
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ADC081500 pdf, datenblatt
Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after
the fall of the clock input for the sampling switch to open. The
Sample/Hold circuit effectively stops capturing the input sig-
nal and goes into the “hold” mode the aperture delay time
(tAD) after the input clock goes low.
APERTURE JITTER (tAJ) is the variation in aperture delay
from sample to sample. Aperture jitter shows up as input
noise.
Bit Error Rate (B.E.R.) is the probability of error and is
defined as the probable number of errors per unit of time
divided by the number of bits seen in that amount of time. A
B.E.R. of 10-18 corresponds to a statistical error in one bit
about every four (4) years.
CLOCK DUTY CYCLE is the ratio of the time that the clock
wave form is at a logic high to the total time of one clock
period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at 1.5 GSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD −
1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH (FPBW) is a measure of the
frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale
input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated from Offset and Full-
Scale Errors:
Positive Gain Error = Offset Error − Positive Full-Scale
Error
Negative Gain Error = −(Offset Error − Negative Full-
Scale Error)
Gain Error = Negative Full-Scale Error − Positive Full-
Scale Error = Positive Gain Error + Negative Gain Error
INTEGRAL NON-LINEARITY (INL) is a measure of the
deviation of each individual code from a straight line through
the input to output transfer function. The deviation of any
given code from this straight line is measured from the
center of that code value. The best fit method is used.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
it is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the
smallest value or weight of all bits. This value is
VFS / 2n
where VFS is the differential full-scale amplitude of 650 mV
or 870 mV as set by the FSR input and "n" is the ADC
resolution in bits, which is 8 for the ADC081500.
LVDS DIFFERENTIAL OUTPUT VOLTAGE (VOD) is the
absolute value of the difference between the VD+ & VD-
outputs; each measured with respect to Ground.
20153146
FIGURE 1.
LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpoint
between the D+ and D- pins output voltage; ie., [(VD+) +(
VD-)]/2.
MISSING CODES are those output codes that are skipped
and will never appear at the ADC outputs. These codes
cannot be reached with any input value.
MSB (MOST SIGNIFICANT BIT) is the bit that has the
largest value or weight. Its value is one half of full scale.
NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of
how far the last code transition is from the ideal 1/2 LSB
above a differential −435 mV with the FSR pin high, or 1/2
LSB above a differential −325 mV with the FSR pin low. For
the ADC081500 the reference voltage is assumed to be
ideal, so this error is a combination of full-scale error and
reference voltage error.
OFFSET ERROR (VOFF) is a measure of how far the mid-
scale point is from the ideal zero voltage differential input.
Offset Error = Actual Input causing average of 8k
samples to result in an average code of 127.5.
OUTPUT DELAY (tOD) is the time delay (in addition to
Pipeline Delay) after the falling edge of CLK+ before the data
update is present at the output pins.
OVER-RANGE RECOVERY TIME is the time required after
the differential input voltages goes from ±1.2V to 0V for the
converter to recover and make a conversion with its rated
accuracy.
PIPELINE DELAY (LATENCY) is the number of input clock
cycles between initiation of conversion and when that data is
presented to the output driver stage. New data is available at
every clock cycle, but the data lags the conversion by the
Pipeline Delay plus the tOD.
POSITIVE FULL-SCALE ERROR (PFSE) is a measure of
how far the last code transition is from the ideal 1-1/2 LSB
below a differential +435 mV with the FSR pin high, or 1-1/2
LSB below a differential +325 mV with the FSR pin low. For
the ADC081500 the reference voltage is assumed to be
ideal, so this error is a combination of full-scale error and
reference voltage error.
POWER SUPPLY REJECTION RATIO (PSRR) can be one
of two specifications. PSRR1 (DC PSRR) is the ratio of the
change in full-scale error that results from a power supply
voltage change from 1.8V to 2.0V. PSRR2 (AC PSRR) is a
measure of how well an a.c. signal riding upon the power
supply is rejected from the output and is measured with a
248 MHz, 50 mVP-P signal riding upon the power supply. It is
the ratio of the output amplitude of that signal at the output to
its amplitude on the power supply pin. PSRR is expressed in
dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal at the output to the
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