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EPCS1 Schematic ( PDF Datasheet ) - Altera Corporation

Teilenummer EPCS1
Beschreibung (EPCS1 - EPCS64) Serial Configuration Devices
Hersteller Altera Corporation
Logo Altera Corporation Logo 




Gesamt 30 Seiten
EPCS1 Datasheet, Funktion
www.DataSheet4U.com
C51014-2.0
Features
Functional
Description
Chapter 4. Serial Configuration
Devices (EPCS1, EPCS4,
EPCS16 & EPCS64) Data Sheet
The serial configuration devices provide the following features:
1-, 4-, 16-, and 64-Mbit flash memory devices that serially configure
Stratix® II FPGAs and the Cyclone™ series FPGAs using the active
serial (AS) configuration scheme
Easy-to-use four-pin interface
Low cost, low pin count and non-volatile memory
Low current during configuration and near-zero standby mode
current
3.3-V operation
Available in 8-pin and 16-pin small outline integrated circuit (SOIC)
package
Enables the Nios® processor to access unused flash memory through
AS memory interface
Re-programmable memory with more than 100,000 erase/program
cycles
Write protection support for memory sectors using status register
bits
In-system programming support with SRunner software driver
Programming support with USB Blaster™ or ByteBlaster™ II
download cables
Additional programming support with the Altera® Programming
Unit (APU) and programming hardware from BP Microsystems,
System General, and other vendors
Software design support with the Altera Quartus® II development
system for Windows-based PCs as well as Sun SPARC station and
HP 9000 Series 700/800
Delivered with the memory array erased (all the bits set to 1)
1 Whenever the term “serial configuration device(s)” is used in
this document, it refers to Altera EPCS1, EPCS4, EPCS16, and
EPCS64 devices.
With SRAM-based devices such as Stratix II FPGAs and the Cyclone
series FPGAs, configuration data must be reloaded each time the device
powers up, the system initializes, or when new configuration data is
needed. Serial configuration devices are flash memory devices with a
Altera Corporation
July 2004
Core Version a.b.c variable
4–1
Preliminary






EPCS1 Datasheet, Funktion
Active Serial FPGA Configuration
Figure 4–2. FPGA Configuration in AS Mode (Serial Configuration Device Programmed Using Download
Cable)
VCC (1) VCC (1) VCC (1)
10 k10 k
Serial
Configuration
Device (2)
DATA
DCLK
nCS
ASDI
10 k
Stratix II or
Cyclone Series FPGA
CONF_DONE
nSTATUS
nCONFIG
nCEO
N.C.
10 k
nCE
DATA0
DCLK
nCSO
ASDO
MSEL[n] n (3)
Pin 1
VCC (1)
4–6 Core Version a.b.c variable
Configuration Handbook, Volume 2
Altera Corporation
July 2004

6 Page









EPCS1 pdf, datenblatt
Serial Configuration Device Memory Access
Figure 4–5. Write Enable Operation Timing Diagram
nCS
DCLK
ASDI
01234567
Operation Code
DATA
High Impedance
Write Disable Operation
The write disable operation code is b'0000 0100, with the MSB listed
first. The write disable operation resets the write enable latch bit, which
is bit 1 in the status register. To prevent the memory from being written
unintentionally, the write enable latch bit is automatically reset when
implementing the write disable operation as well as under the following
conditions:
Power up
Write bytes operation completion
Write status operation completion
Erase bulk operation completion
Erase sector operation completion
Figure 4–6 shows the timing diagram for the write disable operation.
Figure 4–6. Write Disable Operation Timing Diagram
nCS
DCLK
ASDI
01234567
Operation Code
DATA
High Impedance
4–12
Core Version a.b.c variable
Configuration Handbook, Volume 2
Altera Corporation
July 2004

12 Page





SeitenGesamt 30 Seiten
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