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PDF GS88136A Data sheet ( Hoja de datos )
| Número de pieza | GS88136A | |
| Descripción | (GS88118A - GS88136A) Synchronous Burst SRAMs | |
| Fabricantes | GSI | |
| Logotipo |  |
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GS88118A(T/D)/GS88132A(D)/GS88136A(T/D)
100-Pin TQFP & 165-Bump BGA
512K x 18, 256K x 36
Commercial Temp
Industrial Temp
9Mb Synchronous Burst SRAMs
250 MHz–133 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard packages
Functional Description
Applications
The GS88118/36AT/D is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1, E2), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS88118/36AT/D is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88118/36AT/D operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Pipeline tKQ 2.5 2.7 3.0 3.4 3.8 4.0 ns
3-1-1-1 tCycle 4.0 4.4 5.0 6.0 6.7 7.5 ns
Curr (x18) 280 255 230 200 185 165 mA
Curr (x36) 330 300 270 230 215 190 mA
Flow
Through
2-1-1-1
tKQ
tCycle
5.5 6.0 6.5 7.0 7.5 8.5 ns
5.5 6.0 6.5 7.0 7.5 8.5 ns
Curr (x18) 175 165 160 150 145 135 mA
Curr (x36) 200 190 180 170 165 150 mA
Rev: 1.04 3/2005
1/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
1 page  
GS88118A(T/D)/GS88132A(D)/GS88136A(T/D)
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1 2 3 4 5 6 7 8 9 10 11
A NC A E1 BB NC E3 BW ADSC ADV A A
A
B NC A E2 NC BA CK GW G ADSP A NC B
C
NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQA
C
D
NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA
D
E
NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA
E
F
NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA
F
G
NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA
G
H FT MCL NC VDD VSS VSS VSS VDD NC NC ZZ H
J DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC
J
K DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC
K
L DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC
L
M DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC
M
N DQB NC VDDQ VSS NC NC NC VSS VDDQ NC NC
N
P
NC NC
A
A TDI A1 TDO A
A
A
A
P
R LBO NC A A TMS A0 TCK A A A A
R
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.04 3/2005
5/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
5 Page 
GS88118A(T/D)/GS88132A(D)/GS88136A(T/D)
Byte Write Truth Table
Function GW BW BA BB BC BD Notes
Read H H X X X X 1
Read H L H H H H 1
Write byte a
H
L
L
H
H
H 2, 3
Write byte b
H
L
H
L
H
H 2, 3
Write byte c
H
L
H
H
L
H 2, 3, 4
Write byte d
H
L
H
H
H
L 2, 3, 4
Write all bytes
H
L
L
L
L
L 2, 3, 4
Write all bytes
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32/x36 versions.
Rev: 1.04 3/2005
11/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
11 Page | ||
| Páginas | Total 36 Páginas | |
| PDF Descargar | [ Datasheet GS88136A.PDF ] | |
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