PDF GS816136 Data sheet ( Hoja de datos )

Número de pieza	GS816136
Descripción	(GS816118 - GS816136) Sync Burst SRAMs
Fabricantes	GSI
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No Preview Available ! www.DataSheet4U.com GS816118(T/D)/GS816132(D)/GS816136(T/D) GS816118 100-Pin TQFP Pinout (Package T) NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB FT VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 1M X 18 10 11 Top View 72 71 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC Rev: 2.13 11/2004 2/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology 1 page GS816118(T/D)/GS816132(D)/GS816136(T/D) 165 Bump BGA—x32 Common I/O—Top View (Package D) 1 2 3 4 5 6 7 8 9 10 11 A NC A E1 BC BB E3 BW ADSC ADV A NC A B NC A E2 BD BA CK GW G ADSP A NC B C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC NC C D DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB D E DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB E F DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB F G DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB G H FT MCL NC VDD VSS VSS VSS VDD NC ZQ ZZ H J DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA J K DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K L DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L M DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M N NC NC VDDQ VSS NC NC NC VSS VDDQ NC NC N P NC NC A A TDI A1 TDO A A A A17 P R LBO NC A A TMS A0 TCK A A A A R 11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch Rev: 2.13 11/2004 6/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology 5 Page GS816118(T/D)/GS816132(D)/GS816136(T/D) Synchronous Truth Table Operation State Address Used Diagram E1 ADSP ADSC ADV W3 DQ4 Key5 Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L LXXXQ Read Cycle, Begin Burst External R LHLXFQ Write Cycle, Begin Burst External W LHLXTD Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CW H X H L T D Read Cycle, Suspend Burst Current XHHHFQ Read Cycle, Suspend Burst Current HXHHFQ Write Cycle, Suspend Burst Current XHHHTD Write Cycle, Suspend Burst Current HXHHTD Notes: 1. X = Don’t Care, H = High, L = Low 2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 2.13 11/2004 12/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology 11 Page

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