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Teilenummer | GS816132 |
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Beschreibung | (GS816118 - GS816136) Sync Burst SRAMs | |
Hersteller | GSI | |
Logo | ||
Gesamt 30 Seiten www.DataSheet4U.com
GS816118(T/D)/GS816132(D)/GS816136(T/D)
GS816118 100-Pin TQFP Pinout (Package T)
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
FT
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 1M X 18
10
11 Top View
72
71
70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Rev: 2.13 11/2004
2/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS816118(T/D)/GS816132(D)/GS816136(T/D)
165 Bump BGA—x36 Common I/O—Top View (Package D)
1 2 3 4 5 6 7 8 9 10 11
A NC A E1 BC BB E3 BW ADSC ADV A NC A
B NC A E2 BD BA CK GW G ADSP A NC B
C DQPC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPB C
D DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB D
E DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB E
F DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB F
G DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB G
H FT MCL NC VDD VSS VSS VSS VDD NC NC ZZ H
J DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA J
K DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K
L DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L
M DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M
N
DQPD NC VDDQ VSS
NC
NC
NC VSS VDDQ NC DQPA
N
P
NC NC
A
A TDI A1 TDO A
A
A A17
P
R LBO NC A A TMS A0 TCK A A A A
R
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 2.13 11/2004
7/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
6 Page GS816118(T/D)/GS816132(D)/GS816136(T/D)
Simplified State Diagram
X
Deselect
WR
WR
X First Write R
CW CR
First Read
X
CR
W
R
X Burst Write
CR
CW
R
Burst Read
X
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 2.13 11/2004
13/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ GS816132 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
GS816132 | (GS816118 - GS816136) Sync Burst SRAMs | GSI |
GS816132B | (GS816118B - GS816136B) Sync Burst SRAMs | GSI |
GS816136 | (GS816118 - GS816136) Sync Burst SRAMs | GSI |
GS816136B | (GS816118B - GS816136B) Sync Burst SRAMs | GSI |
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