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PDF 82443ZX Data sheet ( Hoja de datos )
| Número de pieza | 82443ZX | |
| Descripción | 440ZX AGPset: Host Bridge/Controller | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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Intel® 440ZX AGPset:
82443ZX Host Bridge/Controller
Datasheet
November 1998
Order Number: 290650-001
1 page  
Contents
1 Architectural Overview ...............................................................................................1-1
2 Signal Description ......................................................................................................2-1
2.1 Host Interface Signals...................................................................................2-1
2.2 DRAM Interface ............................................................................................2-3
2.3 PCI Interface (Primary) .................................................................................2-5
2.4 Primary PCI Sideband Interface ...................................................................2-6
2.5 AGP Interface Signals...................................................................................2-7
2.6 Clocks, Reset, and Miscellaneous ................................................................2-9
2.7 Power-Up/Reset Strap Options...................................................................2-10
3 Register Description...................................................................................................3-1
3.1 I/O Mapped Registers ...................................................................................3-2
3.1.1 CONFADD—Configuration Address Register..................................3-2
3.1.2 CONFDATA—Configuration Data Register .....................................3-3
3.1.3 PM2_CTL—ACPI Power Control 2 Control Register .......................3-4
3.2 PCI Configuration Space Access..................................................................3-4
3.2.1 Configuration Space Mechanism Overview .....................................3-5
3.2.2 Routing the Configuration Accesses to PCI or AGP ........................3-5
3.2.3 PCI Bus Configuration Mechanism Overview ..................................3-6
3.2.3.1 Type 0 Access ....................................................................3-6
3.2.3.2 Type 1 Access ....................................................................3-6
3.2.4 AGP Bus Configuration Mechanism Overview ................................3-6
3.2.5 Mapping of Configuration Cycles on AGP .......................................3-7
3.3 Host-to-PCI Bridge Registers (Device 0) ......................................................3-8
3.3.1 VID—Vendor Identification Register (Device 0).............................3-10
3.3.2 DID—Device Identification Register (Device 0) .............................3-10
3.3.3 PCICMD—PCI Command Register (Device 0) ..............................3-11
3.3.4 PCISTS—PCI Status Register (Device 0) .....................................3-12
3.3.5 RID—Revision Identification Register (Device 0) ..........................3-13
3.3.6 SUBC—Sub-Class Code Register (Device 0) ...............................3-13
3.3.7 BCC—Base Class Code Register (Device 0) ................................3-13
3.3.8 MLT—Master Latency Timer Register (Device 0)..........................3-14
3.3.9 HDR—Header Type Register (Device 0) .......................................3-14
3.3.10 APBASE—Aperture Base Configuration Register (Device 0)........3-14
3.3.11 SVID—Subsystem Vendor Identification Register (Device 0)........3-15
3.3.12 SID—Subsystem Identification Register (Device 0).......................3-16
3.3.13 CAPPTR—Capabilities Pointer Register (Device 0) ......................3-16
3.3.14 NBXCFG—NBX Configuration Register (Device 0) .......................3-16
3.3.15 DRAMC—DRAM Control Register (Device 0) ...............................3-19
3.3.16 DRAMT—DRAM Timing Register (Device 0) ................................3-20
3.3.17 PAM[6:0]—Programmable Attribute Map Registers
(Device 0)3-20
3.3.18 DRB[0:7]—DRAM Row Boundary Registers (Device 0) ................3-22
3.3.19 FDHC—Fixed DRAM Hole Control Register (Device 0) ................3-24
3.3.20 MBSC—Memory Buffer Strength Control Register
(Device 0).......................................................................................3-25
82443ZX Host Bridge Datasheet
v
5 Page 
Architectural Overview
PCI and AGP initiated cycles that target the AGP graphics aperture are also translated using the
AGP aperture translation table. AGP-initiated cycles that target the AGP graphics aperture mapped
in main memory do not require a snoop cycle on the host bus, since the coherency of data for that
particular memory range will be maintained by the software.
DRAM Interface
The 82443ZX integrates a DRAM controller that supports a 64-bit main memory interface. The
DRAM controller supports the following features:
• DRAM type: Extended Data Out (EDO) or Synchronous (SDRAM) DRAM controller
optimized for dual-bank SDRAM organization on a row by row basis
• Memory Size: 8 MB to 256MB with 4 memory rows (two DIMMs)
• Addressing Type: Symmetrical and Asymmetrical addressing
• Memory Modules supported: Single and double density 3.3V DIMMs
• DRAM device technology: 16 Mbit and 64 Mbit
• DRAM Speeds: 60 ns for EDO and 100/66 MHz for synchronous memory (SDRAM).
The Intel® 440ZX AGPset also provides DIMM plug-and-play support via Serial Presence Detect
(SPD) mechanism using the SMBus interface.
AGP Interface
The 82443ZX AGP implementation is compatible with the following:
• The Accelerated Graphics Port Specification, Rev 1.0
• Accelerated Graphics Port Memory Performance Specification, Rev 1.0 (4/12/96)
The 82443ZX supports only a synchronous AGP interface coupling to the 82443ZX core
frequency. The AGP interface can reach a theoretical ~500 MByte/sec transfer rate (i.e., using
133 MHz AGP compliant devices).
PCI Interface
The 82443ZX PCI interface is 3.3V (5V tolerant), 33 MHz Rev. 2.1 compliant and supports up to
four external PCI bus masters in addition to the I/O bridge (PIIX4/PIIX4E). The PCI-to-DRAM
interface can reach over 100 MByte/sec transfer rate for streaming reads and over 120 MBytes/sec
for streaming writes.
System Clocking
The 82443ZX operates the host interface at 66MHz or at 66MHz/100 MHz, the SDRAM/core at
66MHz or at 66MHz/100MHz, PCI at 33 MHz and AGP at 66/133 MHz.
82443ZX Host Bridge Datasheet
1-3
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet 82443ZX.PDF ] | |
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