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Teilenummer | PE9763 |
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Beschreibung | 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer | |
Hersteller | Peregrine Semiconductor | |
Logo | ||
Gesamt 15 Seiten www.DataSheet4U.com
Product Description
Peregrine’s PE9763 is a high performance fractional-N PLL
capable of frequency synthesis up to 3.2 GHz. The device is
designed for superior phase noise performance while providing
an order of magnitude reduction in current consumption, when
compared with the existing commercial space PLLs.
The PE9763 features a 10/11 dual modulus prescaler,
counters, a delta sigma modulator, a phase comparator and a
charge pump as shown in Figure 1. Counter values are
programmable through either a serial interface or directly hard-
wired.
PE9763 is optimized for commercial space applications. Single
Event Latch up (SEL) is physically impossible and Single Event
Upset (SEU) is better than 10-9 errors per bit / day. Fabricated
in Peregrine’s patented UTSi® (Ultra Thin Silicon) CMOS
technology, the PE9763 offers excellent RF performance and
intrinsic radiation tolerance.
Product Specification
PE9763
3.2 GHz Delta-Sigma modulated
Fractional-N Frequency Synthesizer
for Low Phase Noise Applications
Features
• 3.2 GHz operation
• ÷10/11 dual modulus prescaler
• Selectable phase detector or charge
pump output
• Serial or Direct mode access
• Frequency selectivity: Comparison
frequency / 218
• Low power —- 25 - 30 mA at 3V (phase
detector / charge pump)
• Rad-Hard
• Ultra-low phase noise
• 68-lead CQFJ or Die
Figure 1. Block Diagram
Fin
Fin
M8:0
A3:0
R5:0
Pre_en
20
Sdata
Primary
21-bit
Latch
fr
K17:0
Direct
Prescaler
10/11
Secon-
dary
20-bit
Latch
Auxilia-
ry
20-bit
Latch
18
20
18
2
Main
Counter
13
+
19
4
DSM
13
66
R Counter
Phase
Detector
PD_U
PD_D
Charge
Pump
CP
Document No. 70-0140-01 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 15
PE9763
Product Specification
Table 5. DC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
IDD Operational supply current;
Prescaler enabled, charge pump disabled
VDD = 2.85 to 3.15 V
Min Typ Max
25
IDD Operational supply current;
Prescaler enabled, charge pump enabled
VDD = 2.85 to 3.15 V
30
IDD Operational supply current;
Prescaler disabled, charge pump disabled
VDD = 2.85 to 3.15 V
10
IDD Operational supply current;
Prescaler disabled, charge pump enabled
VDD = 2.85 to 3.15 V
15
All Digital inputs: K[17:0], R[5:0], M[8:0], A[3:0], Direct, Pre_en, Rand_en, M2_sel, Cpsel, Enh (contains a 70 kΩ pull-down resistor)
VIH High level input voltage
VDD = 2.85 to 3.15 V
0.7 x VDD
VIL Low level input voltage
VDD = 2.85 to 3.15 V
0.3 x VDD
IIH High level input current
VIH = VDD = 3.15 V
+100
IIL Low level input current
VIL = 0, VDD = 3.15 V
-1
Reference Divider input: fr
IIHR High level input current
VIH = VDD = 3.15 V
+100
IILR Low level input current
Counter and phase detector outputs: PD_D, PD_U
VIL = 0, VDD = 3.15 V
-100
VOLD
Output voltage LOW
Iout = 6 mA
0.4
VOHD
Output voltage HIGH
Iout = -3 mA
VDD - 0.4
Digital test outputs: Dout
VOLD
Output voltage LOW
VOHD
Output voltage HIGH
Charge Pump output: CP
Iout = 200 µA
Iout = -200 µA
VDD - 0.4
0.4
ICP - Source Drive current
VCP = VDD / 2
-2.6 2 -1.4
ICP -Sink
Drive current
VCP = VDD / 2
1.4 2 2.6
ICPL Leakage current
1.0 V < VCP < VDD – 1.0 V
-1
1
ICP - Source Sink vs. source mismatch
vs. ICP - Sink
VCP = VDD / 2
TA = 25° C
25
ICP vs. VCP Output current magnitude variation vs. voltage
1.0 V < VCP < VDD – 1.0 V
TA = 25° C
15
Lock detect outputs: (Cext, LD)
VOLC
Output voltage LOW, Cext
Iout = 0.1 mA
0.4
VOHC
Output voltage HIGH, Cext
Iout = -0.1 mA
VDD - 0.4
VOLLD
Output voltage LOW, LD
Iout = 1 mA
0.4
Units
mA
mA
mA
mA
V
V
µA
µA
µA
µA
V
V
V
V
mA
mA
µA
%
%
V
V
V
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 15
Document No. 70-0140-01 │ UltraCMOS™ RFIC Solutions
6 Page PE9763
Product Specification
Phase Detector and Charge Pump
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, namely PD_U,
and PD_D. If the divided VCO leads the divided
reference in phase or frequency (fp leads fc),
PD_D pulses “low”. If the divided reference leads
the divided VCO in phase or frequency (fc leads
fp), PD_U pulses “low”. The width of either pulse
is directly proportional to phase offset between the
two input signals, fp and fc.
For the UP and DOWN mode, PD_U and PD_D
drive an active loop filter which controls the VCO
tune voltage. The phase detector gain is equal to
VDD / 2 п.
PD_U pulses cause an increase in VCO fre-
quency and PD_D pulses cause a decrease in
VCO frequency, for a positive Kv VCO.
For the charge pump mode, the phase detector
outputs are used internally to drive a tri-state
charge pump. However, the PD_U, and PD_D out-
put pins will be drive statically to GND. The
charge pump will drive a fixed 2 mA of current.
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 kΩ resistor. Connecting Cext to an external
shunt capacitor provides low pass filtering of this
signal. Cext also drives the input of an internal in-
verting comparator with an open drain output.
Thus LD is an “AND” function of PD_U and PD_D.
Figure 5. Typical Phase Noise
A typical phase noise plot is shown below. Phase noise results for “Trace 2” is the average values.
Test Conditions: Fout = 1.9202 GHz, Fcomparison = 20 MHz, MASH 1-1, VDD = 3 V, Temp = 25 C,
Loop bandwidth = 80 KHz.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 12 of 15
Document No. 70-0140-01 │ UltraCMOS™ RFIC Solutions
12 Page | ||
Seiten | Gesamt 15 Seiten | |
PDF Download | [ PE9763 Schematic.PDF ] |
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