PDF PE9702 Data sheet ( Hoja de datos )

Número de pieza	PE9702
Descripción	3.0 GHz Integer-N PLL
Fabricantes	Peregrine Semiconductor
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No Preview Available ! www.DataSheet4U.com Product Description Peregrine’s PE9702 is a high-performance integer-N PLL capable of frequency synthesis up to 3.0 GHz. The device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with existing commercial space PLLs. The PE9702 features a 10/11 dual modulus prescaler, counters and a phase comparator as shown in Figure 1. Counter values are programmable through either a serial or parallel interface and can also be directly hard wired. The PE9702 is optimized for commercial space applications. Single Event Latch up (SEL) is physically impossible and Single Event Upset (SEU) is better than 10-9 errors per bit / day. Fabricated in Peregrine’s patented UTSi® (Ultra Thin Silicon) CMOS technology, the PE9702 offers excellent RF performance and intrinsic radiation tolerance. Figure 1. Block Diagram Fin Prescaler Fin 10 / 11 D(7:0) 8 Sdata Primary 20-bit Latch 20 Pre_en M(6:0) A(3:0) R(3:0) fr Secon- dary 20-bit Latch 20 20 20 16 Main Counter 13 66 R Counter ADVANCE INFORMATION PE9702 3.0 GHz Integer-N PLL for Rad Hard Applications Features • 3.0 GHz operation • ÷10/11 dual modulus prescaler • Internal phase detector • Serial, parallel or hardwired programmable • Ultra-low phase noise • SEU < 10-9 errors / bit-day • 100 Krad (Si) total dose • 44-lead CQFJ fp Phase Detector PD_U PD_D fc PEREGRINE SEMICONDUCTOR CORP.  \| http://www.peregrine-semi.com Copyright  Peregrine Semiconductor Corp. 2003 Page 1 of 15 1 page PE9702 Advance Information Table 2. Absolute Maximum Ratings Symbol VDD VI II IO Tstg Parameter/Conditions Min Max Units Supply voltage Voltage on any input DC into any input DC into any output Storage temperature range -0.3 4.0 -0.3 VDD + 0.3 -10 +10 -10 +10 -65 150 V V mA mA °C Table 3. Operating Ratings Symbol VDD TA Parameter/Conditions Min Max Units Supply voltage Operating ambient temperature range 2.85 3.15 -40 85 V °C Table 4. ESD Ratings Symbol VESD Parameter/Conditions ESD voltage (Human Body Model) – Note 1 Level Units 1000 V Note 1: Periodically sampled, not 100% tested. Tested per MIL- STD-883, M3015 C2 Electrostatic Discharge (ESD) Precautions When handling this UTSi device, observe the same precautions that you would use with other ESD- sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 4. Latch-Up Avoidance Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up. PEREGRINE SEMICONDUCTOR CORP.  \| http://www.peregrine-semi.com Copyright  Peregrine Semiconductor Corp. 2003 Page 5 of 15 5 Page PE9702 Advance Information Figure 4. Parallel Interface Mode Timing Diagram D [7 : 0] M1_WR M2_WR A_WR E_WR tDSU tDHLD tPW tCWR tPW Hop_WR tWRC Figure 5. Serial Interface Mode Timing Diagram Sdata E_WR Sclk tEC S_WR tDSU tDHLD tClkH tClkL tCE tCWR tPW tWRC PEREGRINE SEMICONDUCTOR CORP.  \| http://www.peregrine-semi.com Copyright  Peregrine Semiconductor Corp. 2003 Page 11 of 15 11 Page

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