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PE9701 Schematic ( PDF Datasheet ) - Peregrine Semiconductor

Teilenummer PE9701
Beschreibung Integer-N PLL Rad Hard
Hersteller Peregrine Semiconductor
Logo Peregrine Semiconductor Logo 




Gesamt 13 Seiten
PE9701 Datasheet, Funktion
www.DataSheet4U.com
Product Description
Peregrine’s PE9701 is a high-performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The device
is designed for superior phase noise performance while
providing an order of magnitude reduction in current
consumption, when compared with existing commercial
space PLLs.
The PE9701 features a 10/11 dual modulus prescaler,
counters, and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial or
parallel interface and can also be directly hard wired.
The PE9701 is optimized for commercial space
applications. Single Event Latch up (SEL) is physically
impossible and Single Event Upset (SEU) is better than
10-9 errors per bit / day. It is manufactured on Peregrine’s
UltraCMOS™ process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering
excellent RF performance and intrinsic radiation tolerance.
Figure 1. Block Diagram
Product Specification
PE9701
3000 MHz UltraCMOS™ Integer-N PLL
Rad Hard for Space Applications
Features
3.0 GHz operation
÷10/11 dual modulus prescaler
Internal phase detector with charge
pump
Serial, parallel or hardwired
programmable
Ultra-low phase noise
SEU < 10-9 errors / bit-day
100 Krad (Si) total dose
44-lead CQFJ
Fin Prescaler
Fin 10/11
D(7:0)
8
Sdata
Primary
20-bit
Latch 20
Pre_en
M(6:0)
A(3:0)
R(3:0)
fr
Secon-
dary
20-bit
Latch
20
20
20
16
Main
Counter
13
66
R Counter
fp
PD_U
Phase
Detector
PD_D
Charge
Pump
CP
fc
Document No. 70-0035-02 www.psemi.com
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 13






PE9701 Datasheet, Funktion
PE9701
Product Specification
Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min Max Units
Control Interface and Latches (see Figures 4, 5, 6)
fClk Serial data clock frequency
(Note 1)
10 MHz
tClkH Serial clock HIGH time
30 ns
tClkL Serial clock LOW time
tDSU
Sdata hold time after Sclk rising edge, D[7:0] set-up time to
M1_WR, M2_WR, A_WR, E_WR rising edge
tDHLD
Sdata hold time after Sclk rising edge, D[7:0] hold time to
M1_WR, M2_WR, A_WR, E_WR rising edge
30 ns
10 ns
10 ns
tPW S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
tCWR
Sclk rising edge to S_WR rising edge. S_WR, M1_WR,
M2_WR, A_WR falling edge to Hop_WR rising edge
tCE Sclk falling edge to E_WR transition
tWRC
S_WR falling edge to Sclk rising edge. Hop_WR falling
edge to S_WR, M1_WR, M2_WR, A_WR rising edge
tEC E_WR transition to Sclk rising edge
30 ns
30 ns
30 ns
30 ns
30 ns
tMDO MSEL data out delay after Fin rising edge
CL = 12 pf
8 ns
Main Divider (Prescaler Enabled)
Fin Operating frequency
500
3000
MHz
PFin Input level range
External AC coupling
-5 5 dBm
Main Divider (Prescaler Bypassed)
Fin Operating frequency
50 300 MHz
PFin Input level range
External AC coupling
-5 5 dBm
Reference Divider
fr Operating frequency
(Note 3)
100 MHz
Pfr Reference input power (Note 2)
Single-ended input
-2
dBm
Phase Detector
fc Comparison frequency
(Note 3)
20 MHz
Note 1:
Note 2:
Note 3:
Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk
specification.
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p.
Parameter is guaranteed through characterization only, and is not tested.
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 13
Document No. 70-0035-02 UltraCMOS™ RFIC Solutions

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PE9701 pdf, datenblatt
Figure 9. Package Drawing
44-lead CQFJ
PE9701
Product Specification
All dimensions are in mils
Table 10. Ordering Information
Order Code Part Marking
9701-01
PE9701 ES
9701-11
PE9701
9701-00
PE9701 EK
Description
Engineering Samples
Flight Units
Evaluation Kit
Package
44-pin CQFJ
44-pin CQFJ
Shipping Method
40 units / Tray
40 units / Tray
1 / Box
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 12 of 13
Document No. 70-0035-02 UltraCMOS™ RFIC Solutions

12 Page





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