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WM8987L Schematic ( PDF Datasheet ) - Wolfson Microelectronics

Teilenummer WM8987L
Beschreibung Stereo CODEC
Hersteller Wolfson Microelectronics
Logo Wolfson Microelectronics Logo 




Gesamt 30 Seiten
WM8987L Datasheet, Funktion
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WM8987L
Stereo CODEC for Portable Audio Applications
DESCRIPTION
The WM8987L is a low power, high quality stereo CODEC
designed for portable digital audio applications.
The device integrates complete interfaces to stereo or mono
microphones and a stereo BTL (differential) or single-ended
headset. External component requirements are reduced as
no separate microphone or headphone amplifiers are
required. Advanced on-chip digital signal processing
performs equalisation, 3-D sound enhancement and
automatic level control for the microphone or line input.
The WM8987L can operate as a master or a slave, with
various master clock frequencies including 12 or 24MHz for
USB devices, or standard 256fs rates like 12.288MHz and
24.576MHz. Different audio sample rates such as 96kHz,
48kHz, 44.1kHz are generated directly from the master
clock without the need for an external PLL.
The WM8987L operates at supply voltages down to 1.8V,
although the digital core can operate at voltages down to
1.42V to save power, and the maximum for all supplies is
3.6 Volts. Different sections of the chip can also be powered
down under software control.
The WM8987L is supplied in a very small and thin 4x4mm
COL package, ideal for use in ultra-portable and wearable
systems.
BLOCK DIAGRAM
FEATURES
DAC SNR 98dB, ADC 90dB (‘A’ weighted) at 48kHz, 3.3V
On-chip Headphone Driver
- Single-ended or BTL (differential) drive
- >40mW output power on 16/ 3.3V
- DAC to 32BTL headphone: SNR 86dB, THD -66dB
Complete Stereo / Mono Microphone Interface
- Differential or single-ended mic connection
- Programmable ALC / Noise Gate
Digital Equaliser
Low Power
- Stereo playback 8 mW (1.8V / 1.5V supplies)
- Record and playback 13 mW (1.8V / 1.5V supplies)
Low Supply Voltages
- Analogue 1.8V to 3.6V
- Digital core: 1.42V to 3.6V
- Digital I/O: 1.8V to 3.6V
256fs / 384fs or USB master clock rates: 12MHz, 24MHz
Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48,
88.2, 96kHz generated internally from master clock
4x4mm COL package
Register compatible with WM8750L
APPLICATIONS
Wireless Headsets
Portable Music Player / Recorders
WOLFSON MICROELECTRONICS plc
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Pre-Production, January 2007, Rev 3.0
Copyright 2007 Wolfson Microelectronics plc






WM8987L Datasheet, Funktion
WM8987L
Pre-Production
ELECTRICAL CHARACTERISTICS
Test Conditions
DCVDD = 1.5V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB,
ADCOSR = DACOSR = 1 (64 fs), 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL TEST CONDITIONS
Analogue Inputs (LINPUT1, RINPUT1, LINPUT2, RINPUT2) to ADC out
Full Scale Input Signal Level
(for ADC 0dB Input at 0dB Gain)
VINFS
AVDD = 3.3V
AVDD = 1.8V
Input Resistance
L/RINPUT1 to ADC,
PGA gain = 0dB
L/RINPUT1 to ADC,
PGA gain = +30dB
L/RINPUT1 unused
DC Measurement
MIN
TYP
1.0
0.545
22
1.5
16
MAX
UNIT
V rms
k
L/RINPUT1 unused
17
Input Capacitance
10 pF
Signal to Noise Ratio
SNR
AVDD = 3.3V
80 90
dB
(A-weighted)
AVDD = 1.8V
87
Total Harmonic Distortion
THD
-1dBFs input,
-80 dB
AVDD = 3.3V
0.01 %
-1dBFs input,
-70
AVDD = 1.8V
0.03
ADC Channel Separation
1kHz signal
88 dB
Channel Matching
1kHz signal
0.04 %
DAC to BTL headset drive (left=LOUT2/OUT3, right=ROUT1/ROUT2)
Full scale output voltage
across BTL load
0dBFS
LOUT2-OUT3,
ROUT1-ROUT2
AVDD/1.65
Vrms
Output Power per channel
PO
Output power is very closely correlated with THD; see below.
Total Harmonic Distortion
THD
AVDD=HPVDD=1.8V,
RL=32, PO=5mW
-66 -58
0.05 0.13
dB
%
AVDD=HPVDD =1.8V,
RL=16, PO=5mW
-62
0.08
Signal to Noise Ratio
(A-weighted)
SNR
AVDD=HPVDD =1.8V,
RL=32
80
86
dB
DAC to single-ended headset drive (LOUT2/ROUT2, using capacitors)
Full scale output voltage
0dBFS
LOUT2, ROUT2
AVDD/3.3
Vrms
Output Power per channel
Total Harmonic Distortion
PO
THD
Output power is very closely correlated with THD; see below.
HPVDD=3.3V, RL=32,
PO=5mW
-61 -52
0.09 0.25
dB
%
HPVDD=3.3V, RL=16,
PO=5mW
-60 -52
0.1 0.25
Signal to Noise Ratio
SNR
AVDD=HPVDD =3.3V
92
98
dB
(A-weighted)
DAC to single-ended headset drive (capless, using OUT3 as headphone ground)
Full scale output voltage
0dBFS
LOUT2-OUT3,
ROUT2-OUT3
AVDD/3.3
Vrms
Output Power per channel
PO
Output power is very closely correlated with THD; see below.
Total Harmonic Distortion
THD
HPVDD=3.3V, RL=32,
PO=5mW
-61
0.09
dB
%
HPVDD=3.3V, RL=16,
PO=5mW
-60
0.1
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PP Rev 3.0 January 2007
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WM8987L pdf, datenblatt
WM8987L
Pre-Production
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL MIN TYP MAX UNIT
Bit Clock Timing Information
BCLK rise time (10pF load)
tBCLKR
3 ns
BCLK fall time (10pF load)
tBCLKF
3 ns
BCLK duty cycle (normal mode, BCLK = MCLK/n)
tBCLKDS
50:50
BCLK duty cycle (USB mode, BCLK = MCLK)
tBCLKDS
TMCLKDS
Audio Data Input Timing Information
ADCLRC/DACLRC propagation delay from BCLK falling edge
tDL
10 ns
ADCDAT propagation delay from BCLK falling edge
tDDA
40 ns
DACDAT setup time to BCLK rising edge
tDST 10
ns
DACDAT hold time from BCLK rising edge
tDHT
10
ns
AUDIO INTERFACE TIMING – SLAVE MODE
BCLK
DACLRC/
ADCLRC
DACDAT
ADCDAT
tBCH
tBCL
tBCY
tDS
tDD
tLRH
tDH
tLRSU
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
ADCLRC/DACLRC set-up time to BCLK rising edge
tBCY
tBCH
tBCL
tLRSU
50
20
20
10
ns
ns
ns
ns
ADCLRC/DACLRC hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
ADCDAT propagation delay from BCLK falling edge
tLRH
tDH
tDD
10
10
ns
ns
10 ns
Note:
BCLK period should always be greater than or equal to MCLK period.
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PP Rev 3.0 January 2007
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